{"title":"一种采用阻抗倍增补偿的超低功耗三级放大器,适用于nf范围的容性负载","authors":"Mingqi Sun, Fanghui Yin, Xian Tang","doi":"10.1016/j.mejo.2025.106819","DOIUrl":null,"url":null,"abstract":"<div><div>An impedance multiplication compensation (IMC) technology is presented to stabilize the three-stage amplifier driving nF-range capacitive loads. In the proposed compensation method, a serial multiplied RC impedance is located at output of the first stage to generate a low-frequency (LF) left-half-plane (LHP) zero, which reduces the value of the compensation capacitor and consumes only a small amount of quiescent current. It eliminates the bridge-connecting Miller capacitor between the outputs of the first and third stage, thereby preventing the generation of complex poles and improving the gain-bandwidth (GBW) product. The proposed IMC amplifier is implemented in a standard 180 nm CMOS technology with a core area of 0.0027 mm<sup>2</sup>. Post-layout simulation results demonstrate that, in the worst case, the circuit achieves a gain exceeding 100 dB and a gain-bandwidth product of 0.901 MHz with a capacitive load of 15 nF, while consuming only 13.06 μA of quiescent current.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106819"},"PeriodicalIF":1.9000,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An ultra-low-power three-stage amplifier using impedance multiplication compensation for nF-range capacitive loads\",\"authors\":\"Mingqi Sun, Fanghui Yin, Xian Tang\",\"doi\":\"10.1016/j.mejo.2025.106819\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>An impedance multiplication compensation (IMC) technology is presented to stabilize the three-stage amplifier driving nF-range capacitive loads. In the proposed compensation method, a serial multiplied RC impedance is located at output of the first stage to generate a low-frequency (LF) left-half-plane (LHP) zero, which reduces the value of the compensation capacitor and consumes only a small amount of quiescent current. It eliminates the bridge-connecting Miller capacitor between the outputs of the first and third stage, thereby preventing the generation of complex poles and improving the gain-bandwidth (GBW) product. The proposed IMC amplifier is implemented in a standard 180 nm CMOS technology with a core area of 0.0027 mm<sup>2</sup>. Post-layout simulation results demonstrate that, in the worst case, the circuit achieves a gain exceeding 100 dB and a gain-bandwidth product of 0.901 MHz with a capacitive load of 15 nF, while consuming only 13.06 μA of quiescent current.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":\"165 \",\"pages\":\"Article 106819\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2025-07-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239125002681\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125002681","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
An ultra-low-power three-stage amplifier using impedance multiplication compensation for nF-range capacitive loads
An impedance multiplication compensation (IMC) technology is presented to stabilize the three-stage amplifier driving nF-range capacitive loads. In the proposed compensation method, a serial multiplied RC impedance is located at output of the first stage to generate a low-frequency (LF) left-half-plane (LHP) zero, which reduces the value of the compensation capacitor and consumes only a small amount of quiescent current. It eliminates the bridge-connecting Miller capacitor between the outputs of the first and third stage, thereby preventing the generation of complex poles and improving the gain-bandwidth (GBW) product. The proposed IMC amplifier is implemented in a standard 180 nm CMOS technology with a core area of 0.0027 mm2. Post-layout simulation results demonstrate that, in the worst case, the circuit achieves a gain exceeding 100 dB and a gain-bandwidth product of 0.901 MHz with a capacitive load of 15 nF, while consuming only 13.06 μA of quiescent current.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
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