Kefan Qin , Xinyue Zheng , Jianwei Zhao , Shangzheng Yang , Wei Ma , Weibo Hu
{"title":"基于增量和随机转换技术的命令驱动SAR ADC","authors":"Kefan Qin , Xinyue Zheng , Jianwei Zhao , Shangzheng Yang , Wei Ma , Weibo Hu","doi":"10.1016/j.mejo.2025.106833","DOIUrl":null,"url":null,"abstract":"<div><div>A command-driven 16-bit 500 kS/s successive approximation analog to digital converter (SAR ADC) is proposed to support accurate real-time data acquisition in this paper. The proposed ADC starts conversion upon receiving commands from the master, thereby enabling precise data acquisition and fault diagnosis. The ADC consists of three parts, the 1<sup>st</sup> sub-ADC, the residue amplifier (RA), and the 2<sup>nd</sup> sub-ADC. The 1<sup>st</sup> sub-ADC decomposes its capacitive digital-to-analog converter (CDAC) into incremental CDAC and binary CDAC. An incremental random converting technique is implemented in the 1<sup>st</sup>-CDAC to optimize the linearity and dynamic performance by solving the redundant switching. This technique calculates the effective number of capacitors that need to be flipped, and then uses pseudo-random sequence to flip randomly according to the result. The design is implemented with a 180-nm CMOS technology. Measurement results show that the ADC achieves SNR of 89.5 dB, SNDR of 88.4 dB, and THD of −99.1 dB at a sampling rate of 500 kS/s. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are −0.28/+0.49 LSB and −1.95/+1.8 LSB, respectively. The prototype consumes 6.2 mW and occupies 0.9 mm<sup>2</sup>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106833"},"PeriodicalIF":1.9000,"publicationDate":"2025-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A command-driven SAR ADC with incremental and random converting technique\",\"authors\":\"Kefan Qin , Xinyue Zheng , Jianwei Zhao , Shangzheng Yang , Wei Ma , Weibo Hu\",\"doi\":\"10.1016/j.mejo.2025.106833\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>A command-driven 16-bit 500 kS/s successive approximation analog to digital converter (SAR ADC) is proposed to support accurate real-time data acquisition in this paper. The proposed ADC starts conversion upon receiving commands from the master, thereby enabling precise data acquisition and fault diagnosis. The ADC consists of three parts, the 1<sup>st</sup> sub-ADC, the residue amplifier (RA), and the 2<sup>nd</sup> sub-ADC. The 1<sup>st</sup> sub-ADC decomposes its capacitive digital-to-analog converter (CDAC) into incremental CDAC and binary CDAC. An incremental random converting technique is implemented in the 1<sup>st</sup>-CDAC to optimize the linearity and dynamic performance by solving the redundant switching. This technique calculates the effective number of capacitors that need to be flipped, and then uses pseudo-random sequence to flip randomly according to the result. The design is implemented with a 180-nm CMOS technology. Measurement results show that the ADC achieves SNR of 89.5 dB, SNDR of 88.4 dB, and THD of −99.1 dB at a sampling rate of 500 kS/s. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are −0.28/+0.49 LSB and −1.95/+1.8 LSB, respectively. The prototype consumes 6.2 mW and occupies 0.9 mm<sup>2</sup>.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":\"165 \",\"pages\":\"Article 106833\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2025-08-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239125002826\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125002826","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A command-driven SAR ADC with incremental and random converting technique
A command-driven 16-bit 500 kS/s successive approximation analog to digital converter (SAR ADC) is proposed to support accurate real-time data acquisition in this paper. The proposed ADC starts conversion upon receiving commands from the master, thereby enabling precise data acquisition and fault diagnosis. The ADC consists of three parts, the 1st sub-ADC, the residue amplifier (RA), and the 2nd sub-ADC. The 1st sub-ADC decomposes its capacitive digital-to-analog converter (CDAC) into incremental CDAC and binary CDAC. An incremental random converting technique is implemented in the 1st-CDAC to optimize the linearity and dynamic performance by solving the redundant switching. This technique calculates the effective number of capacitors that need to be flipped, and then uses pseudo-random sequence to flip randomly according to the result. The design is implemented with a 180-nm CMOS technology. Measurement results show that the ADC achieves SNR of 89.5 dB, SNDR of 88.4 dB, and THD of −99.1 dB at a sampling rate of 500 kS/s. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are −0.28/+0.49 LSB and −1.95/+1.8 LSB, respectively. The prototype consumes 6.2 mW and occupies 0.9 mm2.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.