High-performance and robust triple node upset radiation hardened latch design

As the technology node of transistors continues to scale down, integrated circuits are more vulnerable to multiple-node-upset (MNU), like double-node upset (DNU) and triple-node upset (TNU). This paper presents a novel 45 nm CMOS triple-node upset radiation-hardened (TNURH) latch for high performance applications. The latch consists of transmission gates (TGs), four input C-Elements (FICEs), and clock gating-based four input C-Elements (CGFICEs). The proposed latch can self-recover from any node upsets, such as single-node upsets (SNUs), double-node upsets (DNUs), and triple-node upsets (TNUs). According to simulation results, the proposed TNURH latch improves the performance results in terms of average power, D–Q delay, CLK-Q delay, power delay product (PDP), area, and power delay area product (PDAP) up to 37.75%, 23.53%, 0.046%, 52.94%, 36.17%, and 69.61% than the recently reported latch. Furthermore, the process, voltage, and temperature (PVT) variations and the Montecarlo (MC) simulations show that the proposed TNURH latch effectively handles the variations.