通过纳米厚的水溶性聚合物插入在二维材料中的接触工程

IF 4.7 3区 材料科学 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
Ryoichiro Naoi, Durgadevi Elamaran and Daisuke Kiriya*, 
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引用次数: 0

摘要

在二维层状材料中,优化金属触点是薄膜晶体管应用的关键挑战。过渡金属二硫族化合物(TMDCs)是一种被充分研究的材料,具有原子级平面度、高迁移率和大电子质量,使其成为超越硅基晶体管的有希望的候选者。然而,金属接触处的费米能级钉住效应(FLP)仍然是一个关键障碍。到目前为止,二维材料(如六方氮化硼和沉积的氧化物)的插入已被证明可以降低FLP,但这些方法既不可扩展,也不能在室温下进行温和的处理,这是避免TMDCs上形成缺陷所必需的。在这里,我们展示了一种溶液可加工的方法,用于在WSe2晶体管的触点上形成薄的有机聚合物层(nm尺度),以抑制FLP效应。所使用的有机聚合物是聚赖氨酸(PLL)水溶液,关键的表面现象是在器件制造过程中的中间处理过程中,通过简单的浇铸和冲洗在触点上自发形成非常薄的聚合物层。WSe2晶体管的温度相关输运特性和肖特基势垒高度估计表明,插入锁相环层可以有效降低FLP。钉住因子(S)从非锁相环处理的S = - 0.001显著调节到锁相环处理的S = - 0.17,突出了锁相环在减轻FLP和改善界面能对准方面的有效性。这项工作使用了一种可扩展的溶液工艺,仅依赖于PLL聚合物与WSe2表面之间的相互作用。这种方法为提高器件性能提供了一种通用策略,并且可以扩展到其他2D材料。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Contact Engineering in 2D Materials via an nm -Thick Hydrosoluble Polymer Insertion

Contact Engineering in 2D Materials via an nm -Thick Hydrosoluble Polymer Insertion

In 2D layered materials, optimizing the metal contacts is a critical challenge for thin-film transistor applications. Transition metal dichalcogenides (TMDCs) are well-studied materials with atomic-level flatness, high mobility, and large electron mass, making them promising candidates to surpass silicon-based transistors. However, the Fermi level pinning (FLP) effect at the metal contact remains a key barrier. As of now, the insertion of 2D materials such as hexagonal boron nitride and deposited oxides has been demonstrated to reduce FLP, but these methods are neither scalable nor mild procedures near room temperature, which is necessary to avoid defect formation on TMDCs. Here, we demonstrate a solution-processable approach for forming a thin organic polymer layer (nm scale) on the contacts to suppress the FLP effect in WSe2 transistors. The organic polymer used was poly-l-lysine (PLL) in an aqueous solution, and the key surface phenomenon is the spontaneous formation of a very thin polymer layer on the contacts through simple casting and rinsing during an intermediate treatment in the device fabrication process. The temperature-dependent transport characteristics and Schottky barrier height estimations of WSe2 transistors demonstrate that inserting a PLL layer effectively reduces the FLP. The pinning factor (S) is significantly modulated from S = −0.001 in non-PLL-treated devices to −0.17 in PLL-treated devices, highlighting the effectiveness of PLL in mitigating FLP and improving interfacial energy alignment. This work uses a scalable solution process that relies simply on the interaction between the PLL polymer and the surface of WSe2. This approach offers a versatile strategy for improving device performance and can be extended to other 2D materials.

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来源期刊
CiteScore
7.20
自引率
4.30%
发文量
567
期刊介绍: ACS Applied Electronic Materials is an interdisciplinary journal publishing original research covering all aspects of electronic materials. The journal is devoted to reports of new and original experimental and theoretical research of an applied nature that integrate knowledge in the areas of materials science, engineering, optics, physics, and chemistry into important applications of electronic materials. Sample research topics that span the journal's scope are inorganic, organic, ionic and polymeric materials with properties that include conducting, semiconducting, superconducting, insulating, dielectric, magnetic, optoelectronic, piezoelectric, ferroelectric and thermoelectric. Indexed/​Abstracted: Web of Science SCIE Scopus CAS INSPEC Portico
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