A phased-array transceiver in 65 nm CMOS for 6G

The researchers — who are based at the Institute of Science Tokyo, Panasonic Industry, Panasonic System Network R&D Lab, and Shinko Electric Industries — replace the oscillator buffer, which is typically used in such systems and has high power and chip area demands, with an injection-locked tripling phase shifter made using 65 nm node complementary metal–oxide–semiconductor (CMOS) technology. In addition to operating as a phase shifter, the device also functions as a frequency tripler. It is directly connected to the mixer to maximize the voltage amplitude and mixer input. An eight-element module with two transceiver integrated circuits, each with four transceivers, is shown to have a maximum data rate of 56 Gbps at a communication distance of 0.3 m and a 26 dBm effective radiated power at 154 GHz, while having a power consumption of up to 150 mW per element and an area of 8.4 mm × 20 mm.

Original reference: A 150 GHz high-power-density phased-array transceiver in 65nm CMOS for 6G UE module. In Proc. 2025 IEEE Symposium on VLSI Technology & Circuits (2025); https://www.vlsisymposium.org/