Making competitive p-channels from monolayer tungsten diselenide

The researchers — who are based at the Taiwan Semiconductor Manufacturing Company, National Taiwan University, and National Yang Ming Chiao Tung University — developed a systematic approach to optimize channel interfaces and improve transistor performance. To mitigate variability caused by the transfer process, the substrate was pre-treated to make the dielectric interface hydrophilic and then cleaned to remove any residue. A sacrificial contact buffer layer was applied to the WSe₂ surface to prevent lithography-induced defects, and a contact liner was inserted between WSe₂ and palladium electrodes to reduce Fermi level pinning (details on the liner material were not given). The transistors have a 4-nm-thick layer of hafnium oxide (HfO_x) as the dielectric. After a free-radical post-treatment and passivation, the resulting devices exhibited an on-current of 400 μA μm⁻¹ at a drain voltage of −1 V, a subthreshold swing of 72 mV per decade, an on/off ratio of 10⁷ and minimal hysteresis. They also showed no performance degradation after one week of air exposure.

Original reference: Performance step-up in PMOS with monolayer WSe₂ channel. In Proc. 2025 IEEE Symposium on VLSI Technology & Circuits (2025); https://www.vlsisymposium.org/