SPIRAL+: Efficient Signal–Power Integrity Co-Analysis for Interchiplet Links Validation

Chiplet technology has recently emerged as a promising solution to improving chip performance through the modularization of complex designs and communication facilitated by high-speed interchiplet serial links. However, the increasing on-package routing density and data rates of these links introduce complex signal and power integrity challenges, surpassing those encountered in traditional large monolithic chips. Addressing these complexities with efficient analysis and design tools is crucial for maintaining design robustness. In this article, we propose SPIRAL+: signal-power integrity co-analysis framework for high-speed interchiplet serial links validation. The framework employs machine learning (ML) to construct transmitter models and utilizes an impulse response extraction method for modeling the channel and receiver. It then performs signal-power integrity co-analysis through a novel double-edge response-based method, leveraging the developed equivalent models. Additionally, an efficient ML model is crafted to accurately predict eye diagram metrics. The analysis provides valuable insights for design optimization. Experimental results show that SPIRAL+ achieves eye diagrams with a mean relative error of 0.07%–7.47%, while realizing a speedup of $31\times $ – $326\times $ over traditional commercial tools.