A Comprehensive End-to-End Security Framework for Optical On-Chip Networks

The Optical Network-on-Chip (ONoC) offers a promising solution to the challenges of scalability, high power consumption, and limited bandwidth inherent in current Electrical Network-on-Chip (ENoC) architectures. Despite its advantages, ONoC remains susceptible to various security threats, notably hardware Trojans (HTs). The insertion of an HT in any optical station can compromise the tuning circuits of microring resonators (MRs), enabling unauthorized manipulation of the data traversing the waveguides. Once compromised, these MRs can be exploited to intercept, alter, or even obstruct data transmission, thereby posing significant risks to the integrity, authenticity, and confidentiality of the communication. To mitigate such threats, various countermeasures can be employed. These include hardware-based authentication and encryption, physical tamper-proofing of the chip, and strict supply chain management to prevent the insertion of HTs during fabrication. Additionally, regular monitoring and auditing of the ONoC are crucial for detecting suspicious activities and implementing timely mitigation strategies. In this paper, we propose a comprehensive security framework designed to address these vulnerabilities at both the physical and application layers, effectively restricting the malicious activities of compromised MRs. At the physical layer, our approach leverages the deterministic power loss characteristics of ONoCs to identify abnormal MR behavior. Concurrently, at the application layer, we introduce a lightweight encryption scheme to secure inter-node communication, thereby preventing unauthorized access and data tampering within the ONoC. The evaluation showed acceptable area, power, and performance overheads, with an 18.2% increase in average packet latency and a 19.2% rise in the energy-delay (ED) product when integrated with state-of-the-art optical interconnects.