Heewon Paik, Junil Lim, Haengha Seo, Tae Kyun Kim, Jonghoon Shin, Haewon Song, Dong Gun Kim, Woongkyu Lee, Dae Seon Kwon and Cheol Seong Hwang
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Furthermore, the GeO<small><sub>2</sub></small> insertion layer decreases the crystallization temperature of the STO film by ∼100 °C, enhancing film quality and facilitating crystallization through the diffusion of Ge atoms. The decreased thermal budget for fabrication enhances the surface smoothness of the STO layer, resulting in a void-free film. Finally, a Pt/RuO<small><sub>2</sub></small>/STO/GeO<small><sub>2</sub></small>/Ru capacitor is fabricated and optimized by fine-tuning the GeO<small><sub>2</sub></small> layer thickness and annealing temperature, achieving a minimum equivalent oxide thickness of 0.41 nm while ensuring a low leakage current density (<10<small><sup>−7</sup></small> A cm<small><sup>−2</sup></small> at 0.8 V), even at a lowered annealing temperature. This highlights the excellent low-temperature compatibility and scalability of STO with GeO<small><sub>2</sub></small> insertion, making it a promising candidate for next-generation dynamic random access memory capacitor technologies.</p>","PeriodicalId":87,"journal":{"name":"Materials Horizons","volume":" 18","pages":" 7305-7317"},"PeriodicalIF":10.7000,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Enhanced crystallization and dielectric properties of atomic layer deposited SrTiO3 thin films on Ru electrode by inserting GeO2 interfacial layer†\",\"authors\":\"Heewon Paik, Junil Lim, Haengha Seo, Tae Kyun Kim, Jonghoon Shin, Haewon Song, Dong Gun Kim, Woongkyu Lee, Dae Seon Kwon and Cheol Seong Hwang\",\"doi\":\"10.1039/D5MH00611B\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p >This study investigates the effects of a GeO<small><sub>2</sub></small> insertion layer between the SrTiO<small><sub>3</sub></small> (STO) dielectric layer and the Ru thin film bottom electrode on the crystallization behavior and associated electrical properties of the STO layer. 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引用次数: 0
摘要
本研究考察了SrTiO3 (STO)介电层和Ru薄膜底电极之间的GeO2插入层对STO层结晶行为和相关电学性能的影响。厚度为0.6 nm的GeO2薄膜可以抑制STO的异常生长,并通过阻止Ru和生长的STO薄膜之间的氧交换,确保整个STO薄膜厚度上Sr/Ti的化学计量均匀。此外,GeO2插入层使STO薄膜的结晶温度降低了约100℃,提高了薄膜质量,并通过Ge原子的扩散促进了结晶。制造过程中减少的热预算提高了STO层的表面光滑度,从而形成无空洞的薄膜。最后,通过微调GeO2层厚度和退火温度,制备并优化了Pt/RuO2/STO/GeO2/Ru电容器,即使在较低的退火温度下,也能实现0.41 nm的最小等效氧化物厚度,同时确保低泄漏电流密度(0.8 V时-7 a cm-2)。这凸显了STO与GeO2插入的出色低温兼容性和可扩展性,使其成为下一代动态随机存取存储电容器技术的有希望的候选者。
Enhanced crystallization and dielectric properties of atomic layer deposited SrTiO3 thin films on Ru electrode by inserting GeO2 interfacial layer†
This study investigates the effects of a GeO2 insertion layer between the SrTiO3 (STO) dielectric layer and the Ru thin film bottom electrode on the crystallization behavior and associated electrical properties of the STO layer. A GeO2 film as thin as 0.6 nm feasibly suppresses abnormal STO growth and ensures uniform Sr/Ti stoichiometry across the entire STO film thickness by blocking the oxygen exchange between the Ru and growing STO film. Furthermore, the GeO2 insertion layer decreases the crystallization temperature of the STO film by ∼100 °C, enhancing film quality and facilitating crystallization through the diffusion of Ge atoms. The decreased thermal budget for fabrication enhances the surface smoothness of the STO layer, resulting in a void-free film. Finally, a Pt/RuO2/STO/GeO2/Ru capacitor is fabricated and optimized by fine-tuning the GeO2 layer thickness and annealing temperature, achieving a minimum equivalent oxide thickness of 0.41 nm while ensuring a low leakage current density (<10−7 A cm−2 at 0.8 V), even at a lowered annealing temperature. This highlights the excellent low-temperature compatibility and scalability of STO with GeO2 insertion, making it a promising candidate for next-generation dynamic random access memory capacitor technologies.