A 14-bit 2.6GS/s RF sampling pipelined ADC in 28nm CMOS

A 14-bit 2.6 GS/s pipelined ADC in 28 nm CMOS process is presented in this paper. It employs 4-channel interleaved pipelined architecture, where offset, gain and timing mismatch errors are calibrated in background. Input buffer is removed to save power and reduce noise. To relax the ADC driving requirement, the sampling and DAC capacitors are split to reduce nonlinear kick-back. To further reduce power, the residue amplifier employs a P/N complemented input structure and the reference buffer employs a push-pull structure, and they are shared between the 4 sub-ADC channels. This ADC achieves an SNR of 60.2dBFS, an SFDR of 70dBc for 140 MHz input signal. The dynamic performance decreases to 51dBFS SNR and 50.7 dB SFDR when input frequency increases to 2.5 GHz. The ADC can sample 5.5 GHz RF input directly, and maintains stable performance through −55 °C–125 °C temperature range and 500 MS/s ∼3 GS/s sample rate. The ADC consumes 980 mW under 0.9V/1.8V supply and occupies an active area of 6 mm².