A 1.58 pJ/b 9 G bps Reference-Less Clock and Data Recovery Circuit With Sigma Range Detector

A 1.58 pJ/b 9 Gbps half-rate reference-less clock and data recovery (CDR) circuit with a sigma range detector (SRD) is presented. The SRD detects the standard deviation of the reference clock frequency error extracted from random data when the stochastic divider ratio is set to 256. The proposed SRD-based CDR mitigates the trade-off between the divider ratio induced by the randomness of the PRBS and the frequency error. This approach enhances the calculation speed of the frequency loop and improves the accuracy of the extracted frequency by eliminating additional compensation stages, resulting in reduced power consumption. The proposed CDR was fabricated in a 65-nm CMOS technology. The lock-time for PRBS11 is $2.7~\mu $ s, with a rms jitter of 1.1 ps and a peak-to-peak jitter of 16 ps. The active area of the design is 0.0636 mm2, with a power efficiency of 1.58 pJ/b.