一种28纳米9T1C sram CIM宏，具有分层电容加权和两步电容比较adc用于cnn

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-21 DOI:10.1109/TVLSI.2025.3545635

Zhiting Lin;Runru Yu;Yunhao Li;Miao Long;Yu Liu;Jianxing Zhou;Da Huo;Qingchuan Zhu;Yue Zhao;Lintao Chen;Chunyu Peng;Qiang Zhao;Xin Li;Chenghu Dai;Xiulong Wu

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引用次数: 0

摘要

在电荷域内存计算（CIM）宏领域，在保持高吞吐量的同时减少电容器阶梯和模数转换器（ADC）的面积仍然是一个重大挑战。本文简要介绍了一个可调权重的CIM宏，旨在提高卷积神经网络（cnn）的能量效率和面积效率。所提出的架构使用：1)一个定制的9T1C位单元，用于提高传感裕度和双向解耦读端口；2)分层电容加权（HCW）结构，以更小的电容面积和加权时间实现1/2/4位的权重积累；3)两步电容比较adc （tc - adc）读出方案，以提高面积效率和吞吐量。所提出的8 kb静态随机地址存储器（SRAM） CIM宏采用28纳米CMOS技术实现。能量效率为224.4 TOPS/W，面积效率为21.894 TOPS/mm2，在输入为4b、权重为4b的MNIST、CIFAR-10和CIFAR-100数据集上的准确率分别为99.67%、89.13%和67.58%。

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A 28-nm 9T1C SRAM-Based CIM Macro With Hierarchical Capacitance Weighting and Two-Step Capacitive Comparison ADCs for CNNs

In the realm of charge-domain computing-in-memory (CIM) macros, reducing the area of capacitor ladder and analog-to-digital converter (ADC) while maintaining high throughput remains a significant challenge. This brief introduces an adjustable-weight CIM macro designed to enhance both energy efficiency and area efficiency for convolutional neural networks (CNNs). The proposed architecture uses: 1) a customized 9T1C bit cell for sensing margin improvement and bidirectional decoupled read ports; 2) a hierarchical capacitance weighting (HCW) structure that achieves a weight accumulation of 1/2/4 bits with less capacitance area and weighting time; and 3) a two-step capacitive comparison ADCs (TC-ADCs) readout scheme to improve area efficiency and throughput. The proposed 8-kb static random address memory (SRAM) CIM macro is implemented using 28-nm CMOS technology. It can achieve an energy efficiency of 224.4 TOPS/W and an area efficiency of 21.894 TOPS/mm², and the accuracies on MNIST, CIFAR-10, and CIFAR-100 datasets are 99.67%, 89.13%, and 67.58% with a 4-b input and 4-b weight.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.