一种基于TSV错位的三维芯片修复结构

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-21 DOI:10.1109/TVLSI.2025.3565650

Huaguo Liang;Jiahui Xiao;Xianrui Dou;Tianming Ni;Yingchun Lu;Zhengfeng Huang

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引用次数: 0

摘要

作为3d集成电路（3d - ic）的关键部件，硅通孔（tsv）的质量对3d - ic的成品率和可靠性有着重要的影响，尤其是在制造过程中的聚类故障。本文提出了一种基于TSV不对准的修复体系。这种结构通过物理地将信号不连接到最近的TSV，而只连接到彼此相距较远的TSV，从而实现更高的修复率。实验结果表明，对于聚类故障，与现有的同类型修复结构相比，所提结构的平均修复率提高了13.42%。与基于路由器的架构相比，该架构在少于8个集群故障的情况下具有相似的平均修复率，且差异小于0.15%，时延和MUX面积开销分别降低了70.27%和54.17%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A TSV Misalignment-Based Repair Architecture in 3-D Chips

As a critical component of 3-D integrated circuits (3D-ICs), the quality of through-silicon vias (TSVs) significantly impacts the yield and reliability of 3D-ICs, especially the clustered faults during manufacturing. In this article, a repair architecture based on TSV misalignment is proposed. This architecture achieves a higher repair rate by physically connecting the signal not to its closest TSV but only to the TSVs far away from each other. Experimental results show that the average repair rate of the proposed architecture increases by 13.42% compared to the existing repair architectures of the same type for clustered faults. Compared to the router-based architecture, the proposed architecture has a similar average repair rate with less than 0.15% difference in fewer than eight clustered faults, reducing the delay and MUX area overhead by 70.27% and 54.17%, respectively.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.