{"title":"基于rtd的可重复使用无源中间体热监测设计方法","authors":"Andreas Tsiougkos;Vasilis F. Pavlidis","doi":"10.1109/TVLSI.2025.3567824","DOIUrl":null,"url":null,"abstract":"The heterogeneous integration underpinned by several advanced packaging options, such as passive interposers offers a promising direction for future integrated systems. However, the diversity of chiplets integrated in these systems can increase design complexity. A means to mitigate this situation is to reuse interposer fabrics. Consequently, reusable interposers should provide for signaling, power, and thermal issues. This work emphasizes thermal issues by introducing a novel and sufficiently accurate thermal monitoring strategy suitable for reusable passive interposers. The proposed strategy is based on metal resistance temperature detectors (RTDs) as sensors optimally arranged on a fixed rectangular grid supporting the reuse of passive interposers. A step-by-step methodology provides the design and allocation of the sensors across the interposer fabric under temperature precision and area constraints. Diverse benchmark scenarios are investigated with the proposed RTDs, which consume only <inline-formula> <tex-math>$33.6~\\mu \\text {W}$ </tex-math></inline-formula> with a footprint of only <inline-formula> <tex-math>$0.159~\\text {mm}^{2}$ </tex-math></inline-formula>. Simulation results show that the proposed methodology achieves six times (<inline-formula> <tex-math>$6\\times $ </tex-math></inline-formula>) improvement in mean absolute error (MAE) for reconstructed heatmaps over conventional chiplet-based sensors. This improvement is shown for different chiplet placements onto an interposer and for 2.5-D heterogeneous systems, where the integrated components do not include any or sufficient on-chip thermal sensors to provide the required temperature precision.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 7","pages":"1803-1815"},"PeriodicalIF":2.8000,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Design Methodology for Thermal Monitoring of Reusable Passive Interposers With RTDs\",\"authors\":\"Andreas Tsiougkos;Vasilis F. Pavlidis\",\"doi\":\"10.1109/TVLSI.2025.3567824\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The heterogeneous integration underpinned by several advanced packaging options, such as passive interposers offers a promising direction for future integrated systems. However, the diversity of chiplets integrated in these systems can increase design complexity. A means to mitigate this situation is to reuse interposer fabrics. Consequently, reusable interposers should provide for signaling, power, and thermal issues. This work emphasizes thermal issues by introducing a novel and sufficiently accurate thermal monitoring strategy suitable for reusable passive interposers. The proposed strategy is based on metal resistance temperature detectors (RTDs) as sensors optimally arranged on a fixed rectangular grid supporting the reuse of passive interposers. A step-by-step methodology provides the design and allocation of the sensors across the interposer fabric under temperature precision and area constraints. Diverse benchmark scenarios are investigated with the proposed RTDs, which consume only <inline-formula> <tex-math>$33.6~\\\\mu \\\\text {W}$ </tex-math></inline-formula> with a footprint of only <inline-formula> <tex-math>$0.159~\\\\text {mm}^{2}$ </tex-math></inline-formula>. Simulation results show that the proposed methodology achieves six times (<inline-formula> <tex-math>$6\\\\times $ </tex-math></inline-formula>) improvement in mean absolute error (MAE) for reconstructed heatmaps over conventional chiplet-based sensors. This improvement is shown for different chiplet placements onto an interposer and for 2.5-D heterogeneous systems, where the integrated components do not include any or sufficient on-chip thermal sensors to provide the required temperature precision.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":\"33 7\",\"pages\":\"1803-1815\"},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2025-03-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11008706/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11008706/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A Design Methodology for Thermal Monitoring of Reusable Passive Interposers With RTDs
The heterogeneous integration underpinned by several advanced packaging options, such as passive interposers offers a promising direction for future integrated systems. However, the diversity of chiplets integrated in these systems can increase design complexity. A means to mitigate this situation is to reuse interposer fabrics. Consequently, reusable interposers should provide for signaling, power, and thermal issues. This work emphasizes thermal issues by introducing a novel and sufficiently accurate thermal monitoring strategy suitable for reusable passive interposers. The proposed strategy is based on metal resistance temperature detectors (RTDs) as sensors optimally arranged on a fixed rectangular grid supporting the reuse of passive interposers. A step-by-step methodology provides the design and allocation of the sensors across the interposer fabric under temperature precision and area constraints. Diverse benchmark scenarios are investigated with the proposed RTDs, which consume only $33.6~\mu \text {W}$ with a footprint of only $0.159~\text {mm}^{2}$ . Simulation results show that the proposed methodology achieves six times ($6\times $ ) improvement in mean absolute error (MAE) for reconstructed heatmaps over conventional chiplet-based sensors. This improvement is shown for different chiplet placements onto an interposer and for 2.5-D heterogeneous systems, where the integrated components do not include any or sufficient on-chip thermal sensors to provide the required temperature precision.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.