Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates

The objective of this study is to examine how interface trap charges (ITC) influence the logic performance of a p-type heterojunction vertical TFET structure without and with gate overlap (HJVTFET-WOG and HJVTFET-WG). The logic gates can be realized with the help of the HJ-VTFET that uses germanium as the source material. Using HJVTFET-WOG and HJVTFET-WG structures, our simulations have proven that two-input universal logic functions like NAND and NOR gates may be realized. By adjusting the gate-source overlap region and choosing the right silicon body thickness, the suggested vertical TFET is able to perform logic operations. For verifying the universal gate functionality, the HJVTFET drain current characteristic and energy band diagram are analyzed by considering the effect of trapped charges. The tunneling width of logic functions is narrower when the ITC is positive and wider when it is negative, and the effective sub-threshold slopes (SS) have been examined. It has been discovered that positive ITCs can enhance device capabilities, while negative ITCs lead to diminishing functionality. The suggested HJVTFET-WOG structure is a promising structure for implementing the logic gates for digital application under the influence of interface trap charges because its electrical performance is less vulnerable to ITC than HJVTFET-WG.