SRAM- and eDRAM-Based Compute-in-Memory Designs, Accelerators, and Evaluation Frameworks: Macro-Level and System-Level Optimization and Evaluation

Compute-in-memory (CIM) has shown great potential in efficiently processing high-dimensional data over traditional von Neumann architectures, becoming a candidate computing fabric for next-generation AI. This has motivated the rapid development of CIM prototypes and deployments in different approaches, among which SRAM- and eDRAM-based CIM have drawn significant attention due to their flexibility and feasibility. At the time of a decade after the first CIM implementation, it is necessary to review the technical approaches and revisit the new findings behind complicated prototypes. Macro-level innovations such as precise current-based computation and deeply coupled algorithm-circuit co-optimization open up the headroom for efficiency vs. signal-to-noise ratio (SNR) tradeoffs in analog and digital CIM, respectively. Furthermore, diverse architectural configurations integrating CIM macros into systemon- chips have demonstrated scale-out of computing capacity. However, architectural integration of CIM still faces challenges from digital peripherals, memory reloading, and communication. These necessitate hardware-software co-designed mappings and, more importantly, comprehensive and fair evaluation frameworks.