GCN-ABFT:图卷积网络的低成本在线错误检测

IF 2.9 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Christodoulos Peltekis;Giorgos Dimitrakopoulos
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引用次数: 0

摘要

图卷积网络(GCNs)在构建面向图结构数据的机器学习应用中非常流行。这种广泛采用导致了专用GCN硬件加速器的开发。在这项工作中,我们解决了GCN加速器的一个关键架构挑战:如何以最小的计算成本检测随机硬件故障引起的GCN计算中的错误。每个GCN层执行一个图卷积,在数学上相当于乘以三个矩阵,通过两个单独的矩阵乘法计算。现有的基于算法的容错(ABFT)技术可以检查单个矩阵乘法的结果。然而,对于GCN层,这个检查应该执行两次。为了避免这种开销,本工作引入了GCN- abft,它直接计算单个GCN层内整个三矩阵乘积的校验和,为GCN加速器中的错误检测提供了一种经济有效的方法。实验结果表明,对于具有代表性的GCN应用,GCN- abft将校验和计算所需的操作次数平均减少了21%以上。这些节省是在不牺牲故障检测精度的情况下实现的,正如所提出的故障注入分析所证明的那样。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
GCN-ABFT: Low-Cost Online Error Checking for Graph Convolutional Networks
Graph convolutional networks (GCNs) are popular for building machine-learning application for graph-structured data. This widespread adoption led to the development of specialized GCN hardware accelerators. In this work, we address a key architectural challenge for GCN accelerators: how to detect errors in GCN computations arising from random hardware faults with the least computation cost. Each GCN layer performs a graph convolution, mathematically equivalent to multiplying three matrices, computed through two separate matrix multiplications. Existing algorithm-based fault tolerance (ABFT) techniques can check the results of individual matrix multiplications. However, for a GCN layer, this check should be performed twice. To avoid this overhead, this work introduces GCN-ABFT that directly calculates a checksum for the entire three-matrix product within a single GCN layer, providing a cost-effective approach for error detection in GCN accelerators. Experimental results demonstrate that GCN-ABFT reduces the number of operations needed for checksum computation by over 21% on average for representative GCN applications. These savings are achieved without sacrificing fault-detection accuracy, as evidenced by the presented fault-injection analysis.
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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