SubMap:基于子CGRA探测的CGRA局部映射策略

IF 2.9 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Ning Li;Dejian Li;Zhipeng Wu;Peiguang Jing;Sio Hang Pun;Yu Liu
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引用次数: 0

摘要

粗粒度可重构阵列(CGRA)是计算密集型循环内核的优质硬件,具有性能、能效和可重构性的良好平衡。然而,CGRA的效率很大程度上取决于编译器如何将从应用程序内核提取的数据流图(DFG)映射到目标体系结构上。现有的大多数CGRA编译器由于探索空间过大而面临编译时间过长的挑战。为了减少搜索空间和编译时间,我们提出了SubMap,它可以自适应地为目标CGRA中的不同DFGs探索合适的子CGRA,并有效地执行映射过程。实验结果表明,该方法在保证映射质量的前提下,大大缩短了编译时间。在HyCube $4\times 4$上,与Morpher (Pathfinder)和Morpher (SA)相比,SubMap的平均性能分别提高了$9.47 \times $和$11.67 \times $。随着目标CGRA规模的增加,SubMap的性能提升更加明显。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration
Coarse-grained reconfigurable array (CGRA) is a quality hardware for compute-intensive loop kernels, with its excellent balance of performance, energy efficiency, and reconfigurability. However, the efficiency of CGRA depends heavily on how the compiler maps the data flow graph (DFG) extracted from application kernels onto the target architecture. Most existing CGRA compilers encounter the challenge of long compilation times due to excessive exploration space. To reduce the exploration space and compilation time, we propose SubMap, which adaptively explores a suitable sub-CGRA for different DFGs in a target CGRA and efficiently performs the mapping process. The experimental results show that SubMap greatly reduces the compilation time compared to the latest methods while maintaining the mapping quality. On HyCube $4\times 4$ , SubMap has an average performance improvement of $9.47 \times $ and $11.67 \times $ , respectively, compared with Morpher (Pathfinder) and Morpher (SA). As the scale of the target CGRA increases, the performance improvement of SubMap becomes more pronounced.
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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