基于时空图卷积网络的SEU仿真故障注入加速

IF 2.9 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Li Lu;Junchao Chen;Aneesh Balakrishnan;Markus Ulbricht;Milos Krstic
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引用次数: 0

摘要

由于电路的日益复杂,评估电路对单事件干扰(SEU)故障的敏感性变得越来越重要和具有挑战性。基于仿真的故障注入非常耗时,特别是对于高度复杂的电路。本文提出了一种利用时空图卷积网络(STGCNs)预测电路中SEU故障传播结果的新方法。通过将电路结构表示为图形并整合仿真工作负载的时间特征,STGCNs可以从这些时空图形中学习以识别SEU故障传播模式。为了验证该方法,我们在六个评估电路上进行了测试,预测精度达到93%-99%。考虑到这种性能,为了加速基于SEU仿真的故障注入,我们将SEU故障分为三个子集,并使用在训练和验证数据集上微调的STGCN来预测测试数据集中的SEU故障传播,从而消除了模拟的需要并减少了所需的时间。为了找到一种有效的数据集分离方法,我们比较了三种采样方法:1)空间采样(对注入断层进行触发器采样);2)时序采样(故障注入采样时间点);3)混合采样(结合时空采样)。混合采样方法是最有前途的,它优化了效率和精度之间的权衡。这种方法减少了50%的仿真时间,同时在六个评估电路上保持95%以上的精度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Accelerate SEU Simulation-Based Fault Injection With Spatio-Temporal Graph Convolutional Networks
Evaluating the sensitivity of circuits to single event upset (SEU) faults has become increasingly important and challenging due to the growing complexity of circuits. Simulation-based fault injection is time-intensive, particularly for highly complex circuits. This article proposes a novel approach using Spatio-temporal graph convolutional networks (STGCNs) to predict SEU fault propagation results in circuits. By representing circuits’ structure as graphs and integrating temporal features from the simulation workload, STGCNs can learn from these spatio-temporal graphs to identify SEU fault propagation patterns. To validate this method, we test it on six evaluation circuits, achieving a prediction accuracy of 93%–99%. Given this performance, to accelerate SEU simulation-based fault injection, we divide SEU faults into three subsets and use an STGCN fine-tuned on the training and validation dataset to predict SEU fault propagation in the test dataset, eliminating the need for simulation and reducing the required time. To identify an efficient dataset separation method, we compare three sampling methods: 1) spatial sampling (sampling flip-flops for injected faults); 2) temporal sampling (sampling time points for fault injection); and 3) hybrid sampling (incorporating both spatial and temporal sampling). The hybrid sampling approach is the most promising, optimizing the tradeoff between efficiency and accuracy. This approach reduces simulation time by 50% while maintaining accuracy above 95% on the six evaluation circuits.
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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