{"title":"通过Runahead的嵌套推测执行攻击","authors":"Chaoqun Shen;Gang Qu;Jiliang Zhang","doi":"10.1109/TCAD.2025.3526544","DOIUrl":null,"url":null,"abstract":"Runahead execution is an effective microarchitectural level performance boosting technique. It removes the blocking load instruction with long latency and speculatively executes the subsequent instructions with little pipeline modifications. However, the nature of prefetching data and instructions creates potential security risks similar to Spectre and Meltdown. In this work, we present the first comprehensive analysis of the security implications of runahead execution and report a novel attack, named SPECRUN. SPECRUN exploits the unresolved branch predictions within nested speculative execution during runahead execution. It can manipulate the speculative execution window and hence eliminates the major limitation of Spectre-type attacks: the number of executable transient instructions is limited by the small reorder buffer size. Therefore, SPECRUN can improve the exploitability of transient attacks significantly. To demonstrate this, we implement a proof-of-concept attack that can successfully extract secrets from a victim process. We analyze existing defense techniques and propose new ones against SPECRUN. The effectiveness and overhead of these mitigation mechanisms are carefully discussed to shed light on the security vulnerabilities and defense before the adoption of runahead execution on current and future processors.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 7","pages":"2475-2487"},"PeriodicalIF":2.7000,"publicationDate":"2025-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Nested Speculative Execution Attacks via Runahead\",\"authors\":\"Chaoqun Shen;Gang Qu;Jiliang Zhang\",\"doi\":\"10.1109/TCAD.2025.3526544\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Runahead execution is an effective microarchitectural level performance boosting technique. It removes the blocking load instruction with long latency and speculatively executes the subsequent instructions with little pipeline modifications. However, the nature of prefetching data and instructions creates potential security risks similar to Spectre and Meltdown. In this work, we present the first comprehensive analysis of the security implications of runahead execution and report a novel attack, named SPECRUN. SPECRUN exploits the unresolved branch predictions within nested speculative execution during runahead execution. It can manipulate the speculative execution window and hence eliminates the major limitation of Spectre-type attacks: the number of executable transient instructions is limited by the small reorder buffer size. Therefore, SPECRUN can improve the exploitability of transient attacks significantly. To demonstrate this, we implement a proof-of-concept attack that can successfully extract secrets from a victim process. We analyze existing defense techniques and propose new ones against SPECRUN. The effectiveness and overhead of these mitigation mechanisms are carefully discussed to shed light on the security vulnerabilities and defense before the adoption of runahead execution on current and future processors.\",\"PeriodicalId\":13251,\"journal\":{\"name\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"volume\":\"44 7\",\"pages\":\"2475-2487\"},\"PeriodicalIF\":2.7000,\"publicationDate\":\"2025-01-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10829581/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10829581/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Runahead execution is an effective microarchitectural level performance boosting technique. It removes the blocking load instruction with long latency and speculatively executes the subsequent instructions with little pipeline modifications. However, the nature of prefetching data and instructions creates potential security risks similar to Spectre and Meltdown. In this work, we present the first comprehensive analysis of the security implications of runahead execution and report a novel attack, named SPECRUN. SPECRUN exploits the unresolved branch predictions within nested speculative execution during runahead execution. It can manipulate the speculative execution window and hence eliminates the major limitation of Spectre-type attacks: the number of executable transient instructions is limited by the small reorder buffer size. Therefore, SPECRUN can improve the exploitability of transient attacks significantly. To demonstrate this, we implement a proof-of-concept attack that can successfully extract secrets from a victim process. We analyze existing defense techniques and propose new ones against SPECRUN. The effectiveness and overhead of these mitigation mechanisms are carefully discussed to shed light on the security vulnerabilities and defense before the adoption of runahead execution on current and future processors.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.