Synchronous VS asynchronous reconfiguration of Memory Bandwidth Management Schemes: A comparative analysis

Memory bandwidth contention may severely inflate the execution time of tasks co-running on modern Commercial Off-The-Shelf (COTS) multicores. An effective and widely deployed solution to mitigate the problem is bandwidth regulation, a technique to limit the available memory bandwidth for those cores that are not executing time-critical tasks. The granularity at which time-critical activities can be identified at the core level can be in fact even finer than a whole task, and just span smaller memory-critical section (MCS) therein. As the co-presence of MCS and non-critical task portions in the system dynamically changes over time, bandwidth regulators require more or less frequent reconfiguration of their parameters. Similar reconfiguration techniques thus represent a central component of dynamic Memory Bandwidth Management Schemes (MBMS). In particular, the overhead and latency of such a component determine the feasibility and control granularity of the overall bandwidth-regulation solution. The literature extensively covers low-level bandwidth regulation mechanisms and – to some extent – their integration in wider MBMSs, yet no in-depth analysis is currently available of the impact of reconfiguration techniques. This paper addresses this issue by proposing a comparative analysis of the two basic approaches to reconfiguring bandwidth regulators in a system: synchronous and asynchronous schemes. The analysis, performed on a real-world setup with both synthetic and real-world benchmarks, shows that the asynchronous technique improves the control granularity of a bandwidth regulator by a factor of up to 19x, moving from the ms to the $\mu$s scale.