Ziang Zhang;Jianing He;Qin Chen;Xuhao Jiang;Xiangning Fan;Lianming Li
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引用次数: 0
摘要
介绍了一种衰减范围为15.5 db /0.5 db /阶跃的超宽带低损耗数字阶跃衰减器（DSA）。为了降低插入损耗，提出了一种合并衰减单元，实现4-/8-/12 db的衰减。此外，在合并衰减单元中采用了桥式电容，扩大了所提出的DSA的带宽，同时减小了不同衰减状态之间的相位误差。该DSA采用65纳米体CMOS工艺制造，核心面积仅为0.026 mm2。通过测量，在从dc到51.5 GHz的整个工作带宽范围内，它实现了小于5 dB的IL和小于0.25 dB/3.1°的均方根衰减/相位误差。
A DC-51.5 GHz Digital Step Attenuator With Sub-5 dB Insertion Loss and 3.1° RMS Phase Error
This article presents an ultrawideband and low-loss digital step attenuator (DSA) with a 15.5-/0.5-dB attenuation range/step. To reduce the insertion loss (IL), a merged attenuation cell is proposed to realize 4-/8-/12-dB attenuation. Moreover, a bridge capacitor is adopted in the merged attenuation cell to expand the bandwidth of the proposed DSA while reducing the phase error between different attenuation states. The proposed DSA is fabricated with a 65-nm bulk CMOS process with a compact core area of only 0.026 mm2. With measurements, over the entire operating bandwidth from dc to 51.5 GHz, it achieves an IL of less than 5 dB and root-mean-square (rms) attenuation/phase errors of less than 0.25 dB/3.1°, respectively.
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