DTB+:一种增强的数据管理策略,用于有效减少IMR驱动器中的RMW

IF 4.1 2区 计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Fangxing Yu , Chi Zhang , Menghan Li , Zhike Li , Shiqiang Nie , Weiguo Wu
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引用次数: 0

摘要

新兴的交错磁记录(inter隔行磁记录,IMR)技术不仅实现了比SMR更高的存储密度,而且通过将磁道划分为底部磁道和顶部磁道并以交错的方式进行组织,显著降低了重写开销。但是,在磁盘空间利用率高的情况下,频繁更新底层轨道可能会触发大量的读-修改-写(RMW)操作,这会严重降低I/O性能。针对这一问题,本文提出了一种名为DTB+的交错转换层来提高IMR磁盘的写入性能。首先,引入工作负载敏感的航迹热分析机制,实现数据智能放置,降低航迹重写概率;同时,选择性地利用零增量成本区域构建双缓冲区架构,以减少RMW操作。此外,开发了基于强化学习的自适应空间分配引擎,灵活地分配和回收双缓冲区内的空间,提高了磁盘资源利用率。最后,建立一个灵活的被驱逐数据传输区,以延迟干扰数据的回写操作,进一步减少额外的开销。实验结果表明,与目前的研究相比,DTB+可将rmw减少63.00%,将额外I/O操作减少57.41%,将平均写延迟降低37.77%,将尾延迟降低53.95%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
DTB+: An enhanced data management strategy for efficient RMW reduction in IMR drives
The emerging Interlaced Magnetic Recording (IMR) technology not only achieves higher storage density than SMR, but also significantly reduces rewrite overhead by dividing tracks into bottom and top tracks and organizing them in an interlaced fashion. However, frequent updates to the bottom track can trigger a large number of Read-Modify-Write (RMW) operations during high disk space utilization, which can severely degrade the I/O performance. Addressing this issue, this paper proposes an interlaced translation layer named DTB+ to improve the write performance of IMR disks. Firstly, a workload-sensitive track heat analysis mechanism is introduced to intelligently place data to reduce track rewrite probability. Simultaneously, the zero-incremental cost region is selectively used to construct a twin-buffer architecture to reduce RMW operations. In addition, an adaptive space allocation engine based on reinforcement learning was developed to flexibly allocate and reclaim space within the twin-buffer, improving disk resource utilization. Finally, establish a flexible evicted-data transfer zone to delay the writeback operations of interference data, further reducing the additional overhead. Experimental results indicate that compared with the state-of-the-art studies, DTB+ can reduce RMWs by 63.00% and additional I/O operations by 57.41%, decrease the average write latency by 37.77%, and lower the tail latency by 53.95%.
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来源期刊
Journal of Systems Architecture
Journal of Systems Architecture 工程技术-计算机:硬件
CiteScore
8.70
自引率
15.60%
发文量
226
审稿时长
46 days
期刊介绍: The Journal of Systems Architecture: Embedded Software Design (JSA) is a journal covering all design and architectural aspects related to embedded systems and software. It ranges from the microarchitecture level via the system software level up to the application-specific architecture level. Aspects such as real-time systems, operating systems, FPGA programming, programming languages, communications (limited to analysis and the software stack), mobile systems, parallel and distributed architectures as well as additional subjects in the computer and system architecture area will fall within the scope of this journal. Technology will not be a main focus, but its use and relevance to particular designs will be. Case studies are welcome but must contribute more than just a design for a particular piece of software. Design automation of such systems including methodologies, techniques and tools for their design as well as novel designs of software components fall within the scope of this journal. Novel applications that use embedded systems are also central in this journal. While hardware is not a part of this journal hardware/software co-design methods that consider interplay between software and hardware components with and emphasis on software are also relevant here.
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