Simulated annealing, spin-coating, and poling: in silico fabrication of ferroelectric polyvinylidene fluoride polymers on graphene as a model of a low-energy-consumption switching device

Ferroelectric polyvinylidene fluoride (PVDF), particularly its β-phase crystals with well-aligned all-trans polymer chains and prominent polarization in composites with other organic or inorganic materials, has attracted great attention in various areas of energy harvesting, storage, and saving. However, since the β phase is not the most stable polymorph of PVDF, a simple solution casting at a low temperature produces a PVDF film with a limited β-phase content, low crystallinity, and/or high porosity. Additional thermal, mechanical, and electrical controls such as annealing, stretching, spin-coating, and poling are required to maximize both the β-phase content and crystallinity of the PVDF film. Herein, the amorphous-to-β-phase crystallization achieved by such processes is mimicked in silico at the molecular level, revealing the effect of each process on the quality of the processed film. The content of the β-phase crystal, which is negligible after the simulated annealing beyond the melting temperature (300 K to 500 K and back to 300 K), increases to 80% after the SLLOD simulations at a shear velocity of 5.5 m s⁻¹ (i.e., by the simulated spin coating of approximately 3000–5000 rpm) and increases further to 100% when combined with a high electric field of 0.18 GV m⁻¹ (i.e., by the simulated electric poling). The perfectly polarized dipole moments of such β-phase PVDF thin films, when deposited on graphene, can induce electrostatic doping (i.e., create charge carriers) in the underlying graphene, even in a zero electric field, resolving the zero-bandgap (i.e., no-OFF-state) issues of graphene while maintaining its high carrier mobility and low-power operation. Indeed, the current–voltage (I–V) curves mimicked by non-equilibrium Green's function calculations on a model device of a field-effect transistor show a modulation of the doping level and in turn the conductance of graphene, virtually achieving an I_ON/I_OFF ratio of up to 20, when the orientation of the PVDF polarization is flipped by a bias gate voltage sweep. We envision that such devices can eventually lead to low-power-consumption high-ON/OFF-ratio graphene-channel field-effect transistors and non-volatile memories.