Sagarika Chowdhury , Debasish Dhal , Rajat Kumar Pal , Goutam Saha
{"title":"交叉参考数字微流控生物芯片的高级故障检测与定位","authors":"Sagarika Chowdhury , Debasish Dhal , Rajat Kumar Pal , Goutam Saha","doi":"10.1016/j.vlsi.2025.102440","DOIUrl":null,"url":null,"abstract":"<div><div>Cross-referencing digital microfluidic biochips (DMFBs) is becoming increasingly appealing as it significantly reduces the design's pin count. However, routing multiple droplets simultaneously within this architecture presents a challenging task. As a result, detecting multiple faulty electrodes within this setup has gained more attention. This paper introduces an advanced and rigorous offline testing technique that addresses the challenges of electrode interference and dynamic fluidic constraints. Given the need to manage multiple droplets simultaneously throughout the testing process, our approach meticulously considers every fine detail. We account for the time taken to reach pseudo-sources from the source, and from the pseudo-sinks to the sink, in addition to the actual travel time. Testing simulations have been conducted on various 2D grid sizes, with results showing a significant improvement in total detection time compared to some existing methods. This proposed technique successfully overcomes several limitations that previous works encountered.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102440"},"PeriodicalIF":2.5000,"publicationDate":"2025-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Advanced fault detection and localization in cross-referencing digital micro-fluidic biochips\",\"authors\":\"Sagarika Chowdhury , Debasish Dhal , Rajat Kumar Pal , Goutam Saha\",\"doi\":\"10.1016/j.vlsi.2025.102440\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>Cross-referencing digital microfluidic biochips (DMFBs) is becoming increasingly appealing as it significantly reduces the design's pin count. However, routing multiple droplets simultaneously within this architecture presents a challenging task. As a result, detecting multiple faulty electrodes within this setup has gained more attention. This paper introduces an advanced and rigorous offline testing technique that addresses the challenges of electrode interference and dynamic fluidic constraints. Given the need to manage multiple droplets simultaneously throughout the testing process, our approach meticulously considers every fine detail. We account for the time taken to reach pseudo-sources from the source, and from the pseudo-sinks to the sink, in addition to the actual travel time. Testing simulations have been conducted on various 2D grid sizes, with results showing a significant improvement in total detection time compared to some existing methods. This proposed technique successfully overcomes several limitations that previous works encountered.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"104 \",\"pages\":\"Article 102440\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025000975\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025000975","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Advanced fault detection and localization in cross-referencing digital micro-fluidic biochips
Cross-referencing digital microfluidic biochips (DMFBs) is becoming increasingly appealing as it significantly reduces the design's pin count. However, routing multiple droplets simultaneously within this architecture presents a challenging task. As a result, detecting multiple faulty electrodes within this setup has gained more attention. This paper introduces an advanced and rigorous offline testing technique that addresses the challenges of electrode interference and dynamic fluidic constraints. Given the need to manage multiple droplets simultaneously throughout the testing process, our approach meticulously considers every fine detail. We account for the time taken to reach pseudo-sources from the source, and from the pseudo-sinks to the sink, in addition to the actual travel time. Testing simulations have been conducted on various 2D grid sizes, with results showing a significant improvement in total detection time compared to some existing methods. This proposed technique successfully overcomes several limitations that previous works encountered.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.