Dual-K spacer integration in Tree-FETs: A comparative study on leakage reduction and performance enhancement

In this article, the single and dual spacer dielectric performance in a three-channel Tree-FET design is compared in detail for the first time. Different channel lengths extending from 20 nm to 12 nm are systematically evaluated. As device dimensions continue to scale down, traditional spacer designs utilising high-k materials encounter challenges such as increased fringe capacitance and degraded control over leakage. This paper addresses these limitations by investigating a dual-k spacer strategy in Tree-FETs. The device architecture is meticulously optimised, exhibiting a nanosheet height and width of 5 nm and 23 nm, respectively, an inter-bridge height of 5 nm, an inter-bridge width of 8 nm and a channel length of 20 nm–12 nm. To optimise device performance, six dual-k spacer combinations have been meticulously chosen: HfO₂+Air, HfO₂+Si₃N₄, HfO₂+SiO₂, Al₂O₃+Air, Al₂O₃+ Si₃N₄, and Al₂O₃+ SiO₂. The findings unequivocally indicate that the HfO₂+Air dual-k spacer consistently provides superior electrostatic control and markedly boosted DC and analog/RF performance. At a channel length of 20 nm, the HfO₂+Air configuration attains a remarkably low drain-induced barrier lowering (DIBL) of 24.13 mV/V and an exceptionally steep subthreshold swing (SS) of 60.96 mV/dec, surpassing the single-k HfO₂ spacer, which demonstrates a DIBL of 29.02 mV/V and SS of 61.79 mV/dec. Moreover, the device with the HfO₂+Air combination exhibits exceptional analog/RF performance, marked by elevated transconductance (gm), diminished output conductance (gds), and a lower cutoff frequency(f_T). This renders the device exceptionally suitable for high-performance and low-frequency applications. As the channel length increases, the advantages of the dual-k spacer become more apparent, leading to a notable improvement in switching performance and a substantial reduction in leakage current. Furthermore, the HfO₂+Air arrangement routinely attains an I_ON/I_OFF 10⁸, markedly surpassing the I_ON/I_OFF ratio achieved by single-k design. This article highlights the viability of dual-k spacers for the future of semiconductor devices, providing an optimal balance between mitigating short-channel effects and optimising overall device efficiency.