在SpGEMM加速器中动态数据流选择的ML框架

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Sanjali Yadav;Bahar Asgari
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引用次数: 0

摘要

稀疏矩阵-矩阵乘法(SpGEMM)是科学计算、图分析和深度学习等众多领域的关键运算,利用矩阵稀疏性来降低存储和计算成本。然而,稀疏矩阵的不规则结构给性能优化带来了巨大的挑战。现有的硬件加速器通常采用为特定稀疏模式设计的固定数据流,当输入偏离这些假设时,会导致性能下降。随着SpGEMM在各种稀疏性工作负载上的广泛应用,对能够动态调整其数据流方案以适应各种稀疏性模式的加速器的需求也在增长。为了解决这个问题,我们提出了DynaFlow,这是一个基于机器学习的框架,它在任何给定加速器支持的数据流集上进行训练,并学习基于输入稀疏性模式预测最佳数据流。通过利用决策树和深度强化学习,DynaFlow超越了静态数据流选择方法,实现了高达50倍的加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
DynaFlow: An ML Framework for Dynamic Dataflow Selection in SpGEMM Accelerators
Sparse matrix-matrix multiplication (SpGEMM) is a critical operation in numerous fields, including scientific computing, graph analytics, and deep learning, leveraging matrix sparsity to reduce both storage and computation costs. However, the irregular structure of sparse matrices poses significant challenges for performance optimization. Existing hardware accelerators often employ fixed dataflows designed for specific sparsity patterns, leading to performance degradation when the input deviates from these assumptions. As SpGEMM adoption expands across a broad spectrum of sparsity workloads, the demand grows for accelerators capable of dynamically adapting their dataflow schemes to diverse sparsity patterns. To address this, we propose DynaFlow, a machine learning-based framework that trains on the set of dataflows supported by any given accelerator and learns to predict the optimal dataflow based on the input sparsity pattern. By leveraging decision trees and deep reinforcement learning, DynaFlow surpasses static dataflow selection approaches, achieving up to a 50× speedup.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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