Guifang Chen , Xin You , Yeting Xu , Hongjiang Qian , Peng Wang
{"title":"热和振动载荷下TSV显微组织的晶体塑性有限元模拟","authors":"Guifang Chen , Xin You , Yeting Xu , Hongjiang Qian , Peng Wang","doi":"10.1016/j.mejo.2025.106757","DOIUrl":null,"url":null,"abstract":"<div><div>The reliability of through-silicon-via (TSV) microstructures for advanced packaging is crucial. Few studies address their micro-mechanical behavior under thermal cycling, vibration, and thermal-vibration coupled loading. This study uses crystal plasticity finite element method (CPFEM) to investigate plastic deformation in TSVs. Plastic work (<em>W</em><sub><em>p</em></sub>) is used as a fatigue indicator parameter (FIP) for crack initiation prediction. CPFEM simulations show thermo-mechanical coupling causes the highest <em>W</em><sub><em>p</em></sub> amplitude, reducing fatigue life in the low-cycle fatigue (LCF) regime. Vibration loading mainly leads to high-cycle fatigue (HCF) or very high-cycle fatigue (VHCF). Crack initiation patterns vary: thermal cycling and thermo-mechanical coupling cause multi-site nucleation in TSV-Cu and at interfaces, while vibration loading results in single-point initiation at interfaces. Microstructural analysis reveals thermal cycling activates slip systems at quadruple-junction grain boundaries (GBs), with stress concentrations between clustered soft grains surrounded by hard phases. Thermo-mechanical coupling initiates cracks at trident GBs due to hard grain extrusion from yielding soft phases. Interface crack locations under hybrid loading relate to the distribution of the hardest grain. These results highlight the importance of loading type and microstructure in TSV degradation, emphasizing the need for grain boundary engineering and dimensional optimization to mitigate thermo-mechanical fatigue.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106757"},"PeriodicalIF":1.9000,"publicationDate":"2025-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Crystal plasticity finite element simulation of TSV microstructure under thermal and vibration loading\",\"authors\":\"Guifang Chen , Xin You , Yeting Xu , Hongjiang Qian , Peng Wang\",\"doi\":\"10.1016/j.mejo.2025.106757\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>The reliability of through-silicon-via (TSV) microstructures for advanced packaging is crucial. Few studies address their micro-mechanical behavior under thermal cycling, vibration, and thermal-vibration coupled loading. This study uses crystal plasticity finite element method (CPFEM) to investigate plastic deformation in TSVs. Plastic work (<em>W</em><sub><em>p</em></sub>) is used as a fatigue indicator parameter (FIP) for crack initiation prediction. CPFEM simulations show thermo-mechanical coupling causes the highest <em>W</em><sub><em>p</em></sub> amplitude, reducing fatigue life in the low-cycle fatigue (LCF) regime. Vibration loading mainly leads to high-cycle fatigue (HCF) or very high-cycle fatigue (VHCF). Crack initiation patterns vary: thermal cycling and thermo-mechanical coupling cause multi-site nucleation in TSV-Cu and at interfaces, while vibration loading results in single-point initiation at interfaces. Microstructural analysis reveals thermal cycling activates slip systems at quadruple-junction grain boundaries (GBs), with stress concentrations between clustered soft grains surrounded by hard phases. Thermo-mechanical coupling initiates cracks at trident GBs due to hard grain extrusion from yielding soft phases. Interface crack locations under hybrid loading relate to the distribution of the hardest grain. These results highlight the importance of loading type and microstructure in TSV degradation, emphasizing the need for grain boundary engineering and dimensional optimization to mitigate thermo-mechanical fatigue.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":\"162 \",\"pages\":\"Article 106757\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2025-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239125002061\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125002061","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Crystal plasticity finite element simulation of TSV microstructure under thermal and vibration loading
The reliability of through-silicon-via (TSV) microstructures for advanced packaging is crucial. Few studies address their micro-mechanical behavior under thermal cycling, vibration, and thermal-vibration coupled loading. This study uses crystal plasticity finite element method (CPFEM) to investigate plastic deformation in TSVs. Plastic work (Wp) is used as a fatigue indicator parameter (FIP) for crack initiation prediction. CPFEM simulations show thermo-mechanical coupling causes the highest Wp amplitude, reducing fatigue life in the low-cycle fatigue (LCF) regime. Vibration loading mainly leads to high-cycle fatigue (HCF) or very high-cycle fatigue (VHCF). Crack initiation patterns vary: thermal cycling and thermo-mechanical coupling cause multi-site nucleation in TSV-Cu and at interfaces, while vibration loading results in single-point initiation at interfaces. Microstructural analysis reveals thermal cycling activates slip systems at quadruple-junction grain boundaries (GBs), with stress concentrations between clustered soft grains surrounded by hard phases. Thermo-mechanical coupling initiates cracks at trident GBs due to hard grain extrusion from yielding soft phases. Interface crack locations under hybrid loading relate to the distribution of the hardest grain. These results highlight the importance of loading type and microstructure in TSV degradation, emphasizing the need for grain boundary engineering and dimensional optimization to mitigate thermo-mechanical fatigue.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.