Progress and Challenges of 2D van der Waals Multi-Valued Logic Technology

Since the inception of the semiconductor industry, binary logic computing systems have been deeply embedded in our community. However, with the advent of the AI era, the information processing speed of Si CMOS-based binary logic systems has reached its limits with the current technology. For overcoming this, multi-valued logic (MVL) has garnered attention as a high-density computing system that can rapidly process large amounts of information due to there being fewer unit devices and it having low power consumption compared to binary logic. Furthermore, as we approach the 1 nm node era by Moore’s Law, 2D van der Waals (vdW) materials are highlighted for their potential to overcome the limitations of Si materials. Therefore, 2D vdW MVL technology represents the next-generation high-density computing system that is essential for device miniaturization. Here, this review introduces the technological advancements of 2D vdW MVL. First, the history of 2D vdW MVL and the various operation principles are explained for implementing MVL technology. Next, various techniques for implementing vdW MVL were categorized, and the development of these techniques was discussed over time. Finally, this review presents the conclusion by examining the current technological status of vdW MVL and its future prospects.