{"title":"基于聚苯胺/二硫化钼异质结晶体管的设计与分析,以提高模拟性能","authors":"Shivangi Srivastava, Sajal Agarwal","doi":"10.1016/j.micrna.2025.208194","DOIUrl":null,"url":null,"abstract":"<div><div>This study analyzes the performance of heterojunction of a PANI/MoS<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span> transistor through an evaluation of its various electrical characteristics. A comprehensive study is done to critically analyze the proposed device performance in terms of electrical and RF characteristics. Proposed device with channel length of <span><math><mrow><mn>3</mn><mo>.</mo><mn>5</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> exhibited superior performance in terms of threshold voltage (<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>t</mi><mi>h</mi></mrow></msub></math></span>) = −0.39 V, on/off ratio = <span><math><mrow><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>11</mn></mrow></msup></mrow></math></span>, oxide capacitance (<span><math><msub><mrow><mi>C</mi></mrow><mrow><mi>g</mi><mi>g</mi></mrow></msub></math></span>)<span><math><mrow><mo>=</mo><mn>40</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>F/m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> and maximum drain current = <span><math><mrow><mn>27</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span> at comparatively lower gate voltage, i.e. 0.9 V. Maximum drain current can be further increased by 1.7 mA for 32 nm device. With the achieved parameter values, the proposed transistor can be employed for various applications, such as memory storage and analog circuits. However, high on/off ratio and low <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>t</mi><mi>h</mi></mrow></msub></math></span> also ensure its usefulness in different switching and low-power devices. Physical realization of the proposed device is also discussed in detail to provide validation of results.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"206 ","pages":"Article 208194"},"PeriodicalIF":3.0000,"publicationDate":"2025-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and analysis of PANI/MoS2 heterojunction-based transistors for improved analog performance\",\"authors\":\"Shivangi Srivastava, Sajal Agarwal\",\"doi\":\"10.1016/j.micrna.2025.208194\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This study analyzes the performance of heterojunction of a PANI/MoS<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span> transistor through an evaluation of its various electrical characteristics. A comprehensive study is done to critically analyze the proposed device performance in terms of electrical and RF characteristics. Proposed device with channel length of <span><math><mrow><mn>3</mn><mo>.</mo><mn>5</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> exhibited superior performance in terms of threshold voltage (<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>t</mi><mi>h</mi></mrow></msub></math></span>) = −0.39 V, on/off ratio = <span><math><mrow><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>11</mn></mrow></msup></mrow></math></span>, oxide capacitance (<span><math><msub><mrow><mi>C</mi></mrow><mrow><mi>g</mi><mi>g</mi></mrow></msub></math></span>)<span><math><mrow><mo>=</mo><mn>40</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>F/m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> and maximum drain current = <span><math><mrow><mn>27</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span> at comparatively lower gate voltage, i.e. 0.9 V. Maximum drain current can be further increased by 1.7 mA for 32 nm device. With the achieved parameter values, the proposed transistor can be employed for various applications, such as memory storage and analog circuits. However, high on/off ratio and low <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>t</mi><mi>h</mi></mrow></msub></math></span> also ensure its usefulness in different switching and low-power devices. Physical realization of the proposed device is also discussed in detail to provide validation of results.</div></div>\",\"PeriodicalId\":100923,\"journal\":{\"name\":\"Micro and Nanostructures\",\"volume\":\"206 \",\"pages\":\"Article 208194\"},\"PeriodicalIF\":3.0000,\"publicationDate\":\"2025-05-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Micro and Nanostructures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S2773012325001232\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"PHYSICS, CONDENSED MATTER\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micro and Nanostructures","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773012325001232","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"PHYSICS, CONDENSED MATTER","Score":null,"Total":0}
Design and analysis of PANI/MoS2 heterojunction-based transistors for improved analog performance
This study analyzes the performance of heterojunction of a PANI/MoS transistor through an evaluation of its various electrical characteristics. A comprehensive study is done to critically analyze the proposed device performance in terms of electrical and RF characteristics. Proposed device with channel length of exhibited superior performance in terms of threshold voltage () = −0.39 V, on/off ratio = , oxide capacitance () and maximum drain current = at comparatively lower gate voltage, i.e. 0.9 V. Maximum drain current can be further increased by 1.7 mA for 32 nm device. With the achieved parameter values, the proposed transistor can be employed for various applications, such as memory storage and analog circuits. However, high on/off ratio and low also ensure its usefulness in different switching and low-power devices. Physical realization of the proposed device is also discussed in detail to provide validation of results.