{"title":"室温下V2O5薄膜Cr/V2O5/p-Si结二极管的综合电学特性","authors":"Zakir Çaldıran","doi":"10.1007/s10854-025-14913-w","DOIUrl":null,"url":null,"abstract":"<div><p>This study explores the device properties of vanadium pentoxide (V<sub>2</sub>O<sub>5</sub>) thin films in the Cr/V<sub>2</sub>O<sub>5</sub>/p-Si/Al junction diode structure. The experimental setup utilized p-type silicon (p-Si) wafers with a resistivity of 1–10 Ω/cm and a thickness of 400 µm, chemically cleaned using the RCA1 and RCA2 protocols. Aluminum (Al) was deposited on one surface of the wafer as a back contact and annealed at 580 °C to establish ohmic behavior. A 10 nm layer of V<sub>2</sub>O<sub>5</sub> was thermally deposited on the opposite surface and followed by a 100 nm top contact of Cr was deposited by DC sputtering. For comparison, a Cr/p-Si/Al reference device was fabricated under identical conditions, excluding the V<sub>2</sub>O<sub>5</sub> layer. Electrical measurements, including <i>I</i>–<i>V</i> and diode parameter analyses, were performed at room temperature using TE theory, Cheung, and Norde functions. Ideality factor (IF) and barrier height (BH) for the reference diode from the TE method were determined to be 2.03 and 0.58 eV, while the 8 V<sub>2</sub>O<sub>5</sub>-based devices exhibited IF values ranging from 1.89 to 1.96 and BH values between 0.68 and 0.74 eV. The best performing device, designated device 5, achieved an IF value of 1.90 and a BH value of 0.74 eV. In addition, the photodiode properties of this device were analyzed under a solar simulator. These results indicate that the incorporation of the V<sub>2</sub>O<sub>5</sub> interface layer improves the barrier properties of the diode and has potential for advanced rectification and photovoltaic applications. The presence of the series resistance (SR) and interface layer in the device and the inhomogeneity of the BH are also considered as factors contributing to that increase in IF. <i>C</i>–<i>V</i> characterization, another critical technique for understanding the electrical parameters of Schottky-type devices, was used to calculate important parameters such as BH and carrier concentration for the best performing device. Furthermore, <i>G/ω</i>–<i>V</i> and <i>Z</i>–<i>V</i> measurements at different frequencies were analyzed to better understand the electrical properties and surface/interface states of the device with the V<sub>2</sub>O<sub>5</sub> interface.</p></div>","PeriodicalId":646,"journal":{"name":"Journal of Materials Science: Materials in Electronics","volume":"36 15","pages":""},"PeriodicalIF":2.8000,"publicationDate":"2025-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10854-025-14913-w.pdf","citationCount":"0","resultStr":"{\"title\":\"Comprehensive electrical characterization of Cr/V2O5/p-Si junction diode with V2O5 thin film at room temperature\",\"authors\":\"Zakir Çaldıran\",\"doi\":\"10.1007/s10854-025-14913-w\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This study explores the device properties of vanadium pentoxide (V<sub>2</sub>O<sub>5</sub>) thin films in the Cr/V<sub>2</sub>O<sub>5</sub>/p-Si/Al junction diode structure. The experimental setup utilized p-type silicon (p-Si) wafers with a resistivity of 1–10 Ω/cm and a thickness of 400 µm, chemically cleaned using the RCA1 and RCA2 protocols. Aluminum (Al) was deposited on one surface of the wafer as a back contact and annealed at 580 °C to establish ohmic behavior. A 10 nm layer of V<sub>2</sub>O<sub>5</sub> was thermally deposited on the opposite surface and followed by a 100 nm top contact of Cr was deposited by DC sputtering. For comparison, a Cr/p-Si/Al reference device was fabricated under identical conditions, excluding the V<sub>2</sub>O<sub>5</sub> layer. Electrical measurements, including <i>I</i>–<i>V</i> and diode parameter analyses, were performed at room temperature using TE theory, Cheung, and Norde functions. Ideality factor (IF) and barrier height (BH) for the reference diode from the TE method were determined to be 2.03 and 0.58 eV, while the 8 V<sub>2</sub>O<sub>5</sub>-based devices exhibited IF values ranging from 1.89 to 1.96 and BH values between 0.68 and 0.74 eV. The best performing device, designated device 5, achieved an IF value of 1.90 and a BH value of 0.74 eV. In addition, the photodiode properties of this device were analyzed under a solar simulator. These results indicate that the incorporation of the V<sub>2</sub>O<sub>5</sub> interface layer improves the barrier properties of the diode and has potential for advanced rectification and photovoltaic applications. The presence of the series resistance (SR) and interface layer in the device and the inhomogeneity of the BH are also considered as factors contributing to that increase in IF. <i>C</i>–<i>V</i> characterization, another critical technique for understanding the electrical parameters of Schottky-type devices, was used to calculate important parameters such as BH and carrier concentration for the best performing device. Furthermore, <i>G/ω</i>–<i>V</i> and <i>Z</i>–<i>V</i> measurements at different frequencies were analyzed to better understand the electrical properties and surface/interface states of the device with the V<sub>2</sub>O<sub>5</sub> interface.</p></div>\",\"PeriodicalId\":646,\"journal\":{\"name\":\"Journal of Materials Science: Materials in Electronics\",\"volume\":\"36 15\",\"pages\":\"\"},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2025-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://link.springer.com/content/pdf/10.1007/s10854-025-14913-w.pdf\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Materials Science: Materials in Electronics\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10854-025-14913-w\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Materials Science: Materials in Electronics","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10854-025-14913-w","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Comprehensive electrical characterization of Cr/V2O5/p-Si junction diode with V2O5 thin film at room temperature
This study explores the device properties of vanadium pentoxide (V2O5) thin films in the Cr/V2O5/p-Si/Al junction diode structure. The experimental setup utilized p-type silicon (p-Si) wafers with a resistivity of 1–10 Ω/cm and a thickness of 400 µm, chemically cleaned using the RCA1 and RCA2 protocols. Aluminum (Al) was deposited on one surface of the wafer as a back contact and annealed at 580 °C to establish ohmic behavior. A 10 nm layer of V2O5 was thermally deposited on the opposite surface and followed by a 100 nm top contact of Cr was deposited by DC sputtering. For comparison, a Cr/p-Si/Al reference device was fabricated under identical conditions, excluding the V2O5 layer. Electrical measurements, including I–V and diode parameter analyses, were performed at room temperature using TE theory, Cheung, and Norde functions. Ideality factor (IF) and barrier height (BH) for the reference diode from the TE method were determined to be 2.03 and 0.58 eV, while the 8 V2O5-based devices exhibited IF values ranging from 1.89 to 1.96 and BH values between 0.68 and 0.74 eV. The best performing device, designated device 5, achieved an IF value of 1.90 and a BH value of 0.74 eV. In addition, the photodiode properties of this device were analyzed under a solar simulator. These results indicate that the incorporation of the V2O5 interface layer improves the barrier properties of the diode and has potential for advanced rectification and photovoltaic applications. The presence of the series resistance (SR) and interface layer in the device and the inhomogeneity of the BH are also considered as factors contributing to that increase in IF. C–V characterization, another critical technique for understanding the electrical parameters of Schottky-type devices, was used to calculate important parameters such as BH and carrier concentration for the best performing device. Furthermore, G/ω–V and Z–V measurements at different frequencies were analyzed to better understand the electrical properties and surface/interface states of the device with the V2O5 interface.
期刊介绍：
The Journal of Materials Science: Materials in Electronics is an established refereed companion to the Journal of Materials Science. It publishes papers on materials and their applications in modern electronics, covering the ground between fundamental science, such as semiconductor physics, and work concerned specifically with applications. It explores the growth and preparation of new materials, as well as their processing, fabrication, bonding and encapsulation, together with the reliability, failure analysis, quality assurance and characterization related to the whole range of applications in electronics. The Journal presents papers in newly developing fields such as low dimensional structures and devices, optoelectronics including III-V compounds, glasses and linear/non-linear crystal materials and lasers, high Tc superconductors, conducting polymers, thick film materials and new contact technologies, as well as the established electronics device and circuit materials.
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