Impact of gate length on the electrical characteristics of junctionless FDSOI strained SiGe channel p-FinFET

In this work, we present the influence of structure design on the performance of novel fully depleted silicon-on-insulator (FDSOI) SiGe p-type FinFETs. The effects of Ge content, strain in the epitaxial SiGe channel and gate length (L_G) on the device’s electrical characteristics are systematically studied. Among the studied SiGe compositions, Si_0.75Ge_0.25 exhibits superior performance over Si_0.7Ge_0.3, as the latter shows the increased defect density due to strain relaxation, degrading carrier transport and the overall device performance. The strain in the Si_0.75Ge_0.25 channel is tailored to be 0.65% according to the nano beam diffraction (NBD) results, which enhances carrier mobility and drive current (I_on). As the L_G decreases from 500 to 30 nm, the device exhibits a well-balanced trade-off between high drive current and low leakage current, demonstrating the effectiveness of the proposed device structure, while the subthreshold swing (SS) shows a progressive deterioration with decreasing L_G, reflecting the growing impact of short-channel effects and interface states. At L_G = 30 nm, the drain current (I_d), maximum transconductance (G_{m, max}), and I_on/I_off ratio can reach up to 0.19mA/μm, 33.2μS/μm, and 6.9 × 10⁵, respectively. These improvements were attributed to the enhanced hole mobility from strain engineering and the superior electrostatic control of the junctionless architecture. Our work provides valuable insights into the optimization of junctionless FDSOI FinFETs, enhancing their potential for low-power, high-performance semiconductor applications in the beyond Moore era.