具有双模乘法和最大值舍入加法树的RRAM数字内存计算宏

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI:10.1109/TVLSI.2025.3545866

Wang Ye;Hanghang Gao;Zhidao Zhou;Linfang Wang;Weizeng Li;Zhi Li;Jinshan Yue;Xiaoxin Xu;Jianguo Yang;Hongyang Hu;Chunmeng Dou

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引用次数: 0

摘要

由于数字加法树（AT）导致的信号裕度小、器件变化大、能量和面积开销大，基于电阻式存储器（RRAM）实现数字内存计算（DCIM）面临着几个关键挑战。为了解决这些问题，我们提出了一个基于标准铸造厂单晶体管一电阻（1T1R）单元阵列的RRAM DCIM宏，具有：1)双模MAC操作，以实现效率或精度为导向的优化；2)利用边缘增强数字化单元（MEDU）放大信号比；3)最大值舍入AT (MVR-AT)，以减少其功率和面积开销。使用180纳米CMOS工艺演示了测试芯片以验证该概念。在效率导向模式下，其峰值能效EF为63.08 TOPS/W，在精度导向模式下，其最小误差率为1.58%。它们的组合可以满足人工智能计算任务中不同工作负载的要求，在精度损失可以忽略的情况下优化整体功耗。

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An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree

Implementing digital computing-in-memory (DCIM) based on resistive memory (RRAM) faces several critical challenges due to the small signal margin, large device variations, and large energy- and area-overhead induced by the digital adder tree (AT). To address these issues, we propose an RRAM DCIM macro based on the standard foundry one-transistor-one-resistor (1T1R) cell array featuring: 1) dual-mode MAC operation for efficiency- or accuracy-oriented optimization; 2) margin-enhanced digitized unit (MEDU) to amplify the signal ratio; and 3) maximum value rounding AT (MVR-AT) to reduce its power- and area-overhead. A test chip is demonstrated using a 180 nm CMOS process to verify the concept. It achieves a peak energy efficiency (EF) of 63.08 TOPS/W in the efficiency-oriented mode and a minimum error rate of 1.58% in the accuracy-oriented mode. Their combination can meet the requirements of different workloads in AI computing tasks to optimize the overall power consumption with negligible accuracy loss.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.