高密度NAND快闪记忆体的多重ECC研究

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yunpeng Song;Yina Lv;Wentong Li;Jialin Liu;Liang Shi
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引用次数: 0

摘要

采用先进的每单元多比特技术的三维nand闪存由于其高密度而被广泛采用。但是,由于可靠性降低,它面临着读取性能下降和能耗降低的问题。低密度奇偶校验码(Low-density parity-check code, LDPC)通常被用作纠错码(error correction code, ECC)来编码数据并提供容错功能。为了降低成本,通常采用高码率的LDPC。然而,LDPC会导致读取重试操作,当访问的数据没有成功解码时,这种重试引起的性能下降是严重的,特别是对于现代高密度闪存。为了降低低码率LDPC的冗余保护和存储成本,优化读性能,提出了一种可靠性感知差分ECC (READECC)方法。基本思想是考虑到数据访问特性和闪存可靠性特性,采用合适码率的LDPC。首先,根据被访问的频率识别热读。其次,根据可靠性变化的特点,将闪存的寿命划分为三个可靠性周期。随着可靠性周期的变化,LDPC的码率自适应调整,最大限度地减少冗余保护。第三,进一步提出了一种自适应大小的逻辑页面方法,以低存储成本支持纠错能力强(低码率)的LDPC。通过对3-D三层单元nand闪存的仔细设计和评估,READECC以可忽略不计的成本实现了令人鼓舞的优化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Revisiting Multiple ECC on High-Density NAND Flash memory
Three-dimensional nand flash memory using the advanced multibit-per-cell technique is widely adopted due to its high density. However, it faces the problem of deteriorating read performance and energy consumption due to decreased reliability. Low-density parity-check code (LDPC) is typically adopted as an error correction code (ECC) to encode data and provide fault tolerance. To reduce the cost, LDPC with a high code rate is always adopted. However, LDPC will lead to read retry operations when the accessed data are not successfully decoded, and such retry-induced performance degradation is serious, especially for modern high-density flash memory. In this work, a reliability-aware differential ECC (READECC) approach is proposed to reduce redundancy protection and storage cost of LDPC with a low code rate and optimize the read performance. The basic idea is to adopt LDPC with a suitable code rate considering both data access characteristics and flash reliability characteristics. First, hot reads are identified based on the frequency of being accessed. Second, based on the reliability variation characteristics, the life of flash memory is divided into three reliability periods. As the reliability period shifts, the code rate of the LDPC adjusts adaptively to minimize redundancy protection. Third, an adaptive-sized logical page approach is further proposed to support LDPC with strong error correction capability (a low code rate) with a low storage cost. Through careful design and evaluation on 3-D triple-level-cell nand flash memory, READECC achieves encouraging optimizations with a negligible cost.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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