基于亚稳抖动的流水式SAR ADC级间增益非线性数字背景校正

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-03-17 DOI:10.1109/TVLSI.2025.3544825

Le Chen;Yue Cao;Lin Ling;Shubin Liu;Haolin Han

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引用次数: 0

摘要

本文首次提出了一种利用比较器亚稳态校正由级间增益误差和高阶非线性引起的转换误差的数字背景校准技术。该方法通过注入多电平抖动和观察放大器增益变化来校准非线性转换误差。它具有设计简单、精度高、收敛速度快、功耗低等优点。仿真结果证明了该技术的有效性，14位两级流水线逐次逼近寄存器模数转换器（SAR ADC）的信噪比和失真比（SNDR）和无杂散动态范围（SFDR）性能分别从60.4和73.6 dB提高到84.5和110.0 dB。校正算法的收敛速度为80万样本。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC

A digital background calibration technique is proposed in this brief, utilizing comparator metastability to correct conversion errors from interstage gain errors and higher order nonlinearities for the first time. The method calibrates nonlinear conversion errors by injecting multilevel dithers and observing amplifier gain variations. It offers advantages, such as simple design, high accuracy, fast convergence, and low power consumption. Simulation results demonstrate the effectiveness of the technique, with the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) performances of a 14-bit two-stage pipelined successive approximation register analog-to-digital converter (SAR ADC) improving from 60.4 and 73.6 to 84.5 and 110.0 dB, respectively. The convergence speed of the calibration algorithm is 0.8 million samples.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.