Simulation study of a 1200V 4H–SiC lateral MOSFETs with Double-RESURFs technology for reducing saturation current

A 1200V 4H–SiC lateral double-diffused MOSFETs (LDMOS) with embedded auto-adjust JFET (AD-JEFT) and double-reduced surface fields technology is proposed. The AD-JEFT, as the conduction path of electrons from N+ source to the P-well channel, is embedded in P+ well. In the on-state, as the device is pressurized, the increase of depletion charge will reduce the effective channel width of AD-JFET. As a result, the potential barrier of the AD-JFET channel will increase rapidly, making it difficult for electrons to transfer and resulting in a reduction of the saturation current. Compared with the common LDMOS (C-LDMOS), the saturation current (I_dsat) of the proposed LDMOS with AD-JEFT (ADJ-LDMOS) is reduced by 53.3 %. Meanwhile, the short circuit capability is improved by 110.5 %. In addition, the top P-type region of ADJ-LDMOS is divided into a higher doped P-top region and a lower doped P-top2 region, which greatly improves the blocking ability. The breakdown voltage was increased by 21.9 % without increasing the specific on-resistance (R_on,sp).