A flexible SoC for quantum key distribution post-processing based on RISC-V processor

In the domain of quantum-secure communications, post-processing emerges as a critical mechanism to ensure the security and integrity of the generated keys generated by quantum key distribution (QKD). However, existing post-processing frameworks often lack universality, being highly tailored to single-algorithm implementations and frequently neglecting key aspects such as system scalability and integration. To address these limitations, we present a novel system-on-chip (SoC) architecture for QKD post-processing, built around a co-designed framework featuring a RISC-V soft-core processor. This architecture incorporates core functionalities essential to QKD post-processing, including privacy amplification, information reconciliation, and high-speed communication interfaces. By leveraging the flexibility of the open-source RISC-V instruction set, the system achieves enhanced adaptability and energy efficiency. Additionally, a separated-bus architecture is employed, decoupling data and instruction buses to optimize data transfer efficiency and overall system performance, paving the way for scalable and high-throughput quantum communication systems. The system is deployed on the Xilinx Kintex Ultrascale series development board. At the Bob side, with a frame length of 16 384, the information reconciliation module and the privacy amplification module achieves throughputs of 29.73 Mbps and 131.07 Mbps, respectively.