SOT-MRAM-based true in-memory computing architecture for approximate multiplication

The in-memory computing (IMC) paradigm emerges as an effective solution to break the bottlenecks of conventional von Neumann architecture. In the current work, an approximate multiplier in spin-orbit torque magnetoresistive random access memory (SOT-MRAM) based true IMC (STIMC) architecture was presented, where computations were performed natively within the cell array instead of in peripheral circuits. Firstly, basic Boolean logic operations were realized by utilizing the feature of unipolar SOT device. Two majority gate-based imprecise compressors and an ultra-efficient approximate multiplier were then built to reduce the energy and latency. An optimized data mapping strategy facilitating bit-serial operations with an extensive degree of parallelism was also adopted. Finally, the performance enhancements by performing our approximate multiplier in image smoothing were demonstrated. Detailed simulation results show that the proposed 8 × 8 approximate multiplier could reduce the energy and latency at least by 74.2% and 44.4% compared with the existing designs. Moreover, the scheme could achieve improved peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM), ensuring high-quality image processing outcomes.