A Fusion of ReLU and upSample Function With Store in VTA for Higher Throughput of Network Inferencing

The TVM–versatile tensor accelerator (VTA) stack combines hardware–software co-design with operator-level optimizations but relies on ARM processors for auxiliary functions like ReLU and upSample, causing data-transfer bottlenecks and inefficiencies. To address this, we propose fusion VTA (FVTA), integrating ReLU and upSample into the RTL-based Store module with a newly designed instruction set and lightweight C++ runtime. This ensures seamless compatibility with existing VTA modules and eliminates ARM dependence. Evaluated on YOLOv3 with a Xilinx ZCU104 board, FVTA achieves a 195 ms frame processing time for 256 × 256 RGB images—4% faster than EVTA. This work highlights how combining the flexible TVM–VTA stack with optimized circuit-level design can significantly enhance inference efficiency.