Impact of Process Variation on DC and Analog Characteristics of 2 nm Forksheet FET

As semiconductor technology advances from MOSFET to gate-all-around FETs, new structures such as Nanosheet FET (NSFET) and Forksheet FET (FSFET) are gaining attention for sub-5 nm technology nodes. These devices offer superior gate control and high packing density. FSFET features nFET and pFET devices on either side of a dielectric wall, which is compatible with the existing CMOS lateral integration process. In this work, the junctionless FSFET, with bottom dielectric isolation (BDI) is used in studying the DC and RF performance. Additionally, we vary the sheet width and dielectric wall material (SiO₂ and SiN) to observe the effects on the performance of FSFET. Furthermore, the impact of the variation of dielectric wall width on the terminal characteristics is studied. Results reveal that increasing the sheet width enhances ON current (\({I}_{ON}\)), transconductance (\({g}_{m}\)), output conductance (\({g}_{ds}\)), unity current gain frequency (\({f}_{T}\)), and maximum oscillation frequency (f_max), while intrinsic gain (\({A}_{vo}\)) and intrinsic delay (τ) are negatively affected. Silicon oxide, used as the dielectric wall material, demonstrates lower leakage currents and better performance when compared to silicon nitride as the dielectric wall material. It is found that leakages are substantially controlled in FSFET and also have lower subthreshold swing and DIBL compared to NSFET at the same technology node. These findings provide valuable insights into optimizing FSFETs for high-speed and analog applications.