{"title":"亚纳米硅基无结双金属栅极全能场效应晶体管结构中增强太赫兹性能和短通道完整性的HfO2/SiO2间隔层氧化物宽度优化：TCAD方法","authors":"Shekhar Yadav, Pooja Srivastava, C.M.S. Negi","doi":"10.1016/j.nwnano.2025.100114","DOIUrl":null,"url":null,"abstract":"<div><div>This research evaluates the suitability of silicon-based Gate-All-Around Metal Oxide Semiconductor Field Effect Transistor (GAA MOSFET) architectures with HfO<sub>2</sub>/SiO<sub>2</sub> oxide stack spacers for high-frequency applications. Comprehensive analyses of all essential parameters, including transconductance (g<sub>m</sub>), unity gain cut-off frequency (f<sub>T</sub>), drain conductance (g<sub>d</sub>), intrinsic gain (g<sub>m</sub>/g<sub>d</sub>), transconductance efficiency (g<sub>m</sub>/I<sub>D</sub>), Ion to Ioff ratio (I<sub>on</sub>/I<sub>off</sub>), gate capacitance (C<sub>gg</sub>), and transfer characteristics, were conducted through rigorous TCAD simulations. To ensure the structure's scalability and demonstrate short-channel immunity, Drain Induced Barrier Lowering (DIBL) analysis was performed. Additionally, subthreshold swing (SS) analysis was conducted to prove the power efficiency of the device. The analyses conducted are crucial for evaluating the characteristics of devices when scaled to the nanoscale dimensions. A spacer oxide, composed of a stack of conventional material silicon dioxide (SiO<sub>2</sub>) and the high-k material hafnium oxide (HfO<sub>2</sub>), was incorporated to enhance device performance by improving gate control. It was established that increasing the length of the spacer oxide enhances the effectiveness of the devices in high-frequency ranges. The assessed structures are employed with the Junctionless MOSFET architectures to demonstrate the feasibility of simpler fabrication and improved performance. The results show that the best width for the spacer oxide has a big impact on how well sub-100 nm GAA MOSFETs work at high frequencies, resist short-channel effects, and can be made smaller, making them a good choice for current and future high-frequency electronic devices. These findings provide valuable insights into the development and design of GAA MOSFETs for delivering improved high-speed and low-power devices.</div></div>","PeriodicalId":100942,"journal":{"name":"Nano Trends","volume":"10 ","pages":"Article 100114"},"PeriodicalIF":0.0000,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"HfO2/SiO2 spacer oxide width optimization for enhanced terahertz performance and short-channel integrity in sub-nm silicon based junctionless dual metal gate-all-around FET architectures: A TCAD approach\",\"authors\":\"Shekhar Yadav, Pooja Srivastava, C.M.S. Negi\",\"doi\":\"10.1016/j.nwnano.2025.100114\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This research evaluates the suitability of silicon-based Gate-All-Around Metal Oxide Semiconductor Field Effect Transistor (GAA MOSFET) architectures with HfO<sub>2</sub>/SiO<sub>2</sub> oxide stack spacers for high-frequency applications. Comprehensive analyses of all essential parameters, including transconductance (g<sub>m</sub>), unity gain cut-off frequency (f<sub>T</sub>), drain conductance (g<sub>d</sub>), intrinsic gain (g<sub>m</sub>/g<sub>d</sub>), transconductance efficiency (g<sub>m</sub>/I<sub>D</sub>), Ion to Ioff ratio (I<sub>on</sub>/I<sub>off</sub>), gate capacitance (C<sub>gg</sub>), and transfer characteristics, were conducted through rigorous TCAD simulations. To ensure the structure's scalability and demonstrate short-channel immunity, Drain Induced Barrier Lowering (DIBL) analysis was performed. Additionally, subthreshold swing (SS) analysis was conducted to prove the power efficiency of the device. The analyses conducted are crucial for evaluating the characteristics of devices when scaled to the nanoscale dimensions. A spacer oxide, composed of a stack of conventional material silicon dioxide (SiO<sub>2</sub>) and the high-k material hafnium oxide (HfO<sub>2</sub>), was incorporated to enhance device performance by improving gate control. It was established that increasing the length of the spacer oxide enhances the effectiveness of the devices in high-frequency ranges. The assessed structures are employed with the Junctionless MOSFET architectures to demonstrate the feasibility of simpler fabrication and improved performance. The results show that the best width for the spacer oxide has a big impact on how well sub-100 nm GAA MOSFETs work at high frequencies, resist short-channel effects, and can be made smaller, making them a good choice for current and future high-frequency electronic devices. These findings provide valuable insights into the development and design of GAA MOSFETs for delivering improved high-speed and low-power devices.</div></div>\",\"PeriodicalId\":100942,\"journal\":{\"name\":\"Nano Trends\",\"volume\":\"10 \",\"pages\":\"Article 100114\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2025-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Nano Trends\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S2666978125000431\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nano Trends","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2666978125000431","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
HfO2/SiO2 spacer oxide width optimization for enhanced terahertz performance and short-channel integrity in sub-nm silicon based junctionless dual metal gate-all-around FET architectures: A TCAD approach
This research evaluates the suitability of silicon-based Gate-All-Around Metal Oxide Semiconductor Field Effect Transistor (GAA MOSFET) architectures with HfO2/SiO2 oxide stack spacers for high-frequency applications. Comprehensive analyses of all essential parameters, including transconductance (gm), unity gain cut-off frequency (fT), drain conductance (gd), intrinsic gain (gm/gd), transconductance efficiency (gm/ID), Ion to Ioff ratio (Ion/Ioff), gate capacitance (Cgg), and transfer characteristics, were conducted through rigorous TCAD simulations. To ensure the structure's scalability and demonstrate short-channel immunity, Drain Induced Barrier Lowering (DIBL) analysis was performed. Additionally, subthreshold swing (SS) analysis was conducted to prove the power efficiency of the device. The analyses conducted are crucial for evaluating the characteristics of devices when scaled to the nanoscale dimensions. A spacer oxide, composed of a stack of conventional material silicon dioxide (SiO2) and the high-k material hafnium oxide (HfO2), was incorporated to enhance device performance by improving gate control. It was established that increasing the length of the spacer oxide enhances the effectiveness of the devices in high-frequency ranges. The assessed structures are employed with the Junctionless MOSFET architectures to demonstrate the feasibility of simpler fabrication and improved performance. The results show that the best width for the spacer oxide has a big impact on how well sub-100 nm GAA MOSFETs work at high frequencies, resist short-channel effects, and can be made smaller, making them a good choice for current and future high-frequency electronic devices. These findings provide valuable insights into the development and design of GAA MOSFETs for delivering improved high-speed and low-power devices.
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