A survey on routing algorithm and router microarchitecture of three-dimensional Network-on-Chip

The continuous advancement of modern integrated circuits has facilitated the emergence of three-dimensional Networks-on-Chip (3D NoC), characterized by their direct vertical inter-layer electrical connections, which significantly enhance interconnect density. The performance and efficiency of 3D NoC architectures are jointly influenced by routing algorithms and router microarchitectures, which exhibit a symbiotic and complementary relationship. Routing algorithms are instrumental in determining the pathways for data packet transmission, profoundly influencing network latency, throughput, and reliability. Meanwhile, the router executes these algorithms, optimizing overall system efficiency through judicious resource allocation and effective data processing management. In this survey, we categorize routing algorithms according to various criteria, providing a detailed analysis of oblivious, adaptive, and hybrid oblivious-adaptive algorithms based on their degrees of adaptivity. Furthermore, we examine router microarchitectures, classifying them into buffered, bufferless, and hybrid buffered-bufferless designs, depending on whether buffering mechanisms are employed. This survey offers a comprehensive analysis of the co-evolution and co-design of routing algorithms and router microarchitectures, emphasizing that the alignment of an optimal routing algorithm with the appropriate microarchitecture is critical for better 3D NoC performance.