一种适用于低电压和低面积应用的16nm转换完成检测方案的感测放大器触发器

IF 0.7 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Electronics Letters Pub Date : 2025-04-30 DOI:10.1049/ell2.70265

Jin-Fa Lin, Cheng-Hsueh Yang

{"title":"一种适用于低电压和低面积应用的16nm转换完成检测方案的感测放大器触发器","authors":"Jin-Fa Lin, Cheng-Hsueh Yang","doi":"10.1049/ell2.70265","DOIUrl":null,"url":null,"abstract":"<p>A low-power sense-amplifier (SA) flip-flop (FF) with transition completion detection is proposed for low-voltage applications. By replacing logic functions, the proposed detection circuit can be efficiently integrated into SA and latch designs, leading to a significant reduction in area while reducing power and ensuring reliable operation at low voltage. The post-layout simulation results implemented in the TSMC 16-nm CMOS process show that, at an operating voltage of 0.4 V and a switching activity of 25%, the proposed design achieves a 25.8% reduction in power and up to 38.7% area savings compared to previous designs.</p>","PeriodicalId":11556,"journal":{"name":"Electronics Letters","volume":"61 1","pages":""},"PeriodicalIF":0.7000,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/ell2.70265","citationCount":"0","resultStr":"{\"title\":\"A Sense-Amplifier Flip-Flop With Transition Completion Detection Scheme in 16nm for Low-Voltage and Low-Area Applications\",\"authors\":\"Jin-Fa Lin, Cheng-Hsueh Yang\",\"doi\":\"10.1049/ell2.70265\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>A low-power sense-amplifier (SA) flip-flop (FF) with transition completion detection is proposed for low-voltage applications. By replacing logic functions, the proposed detection circuit can be efficiently integrated into SA and latch designs, leading to a significant reduction in area while reducing power and ensuring reliable operation at low voltage. The post-layout simulation results implemented in the TSMC 16-nm CMOS process show that, at an operating voltage of 0.4 V and a switching activity of 25%, the proposed design achieves a 25.8% reduction in power and up to 38.7% area savings compared to previous designs.</p>\",\"PeriodicalId\":11556,\"journal\":{\"name\":\"Electronics Letters\",\"volume\":\"61 1\",\"pages\":\"\"},\"PeriodicalIF\":0.7000,\"publicationDate\":\"2025-04-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://onlinelibrary.wiley.com/doi/epdf/10.1049/ell2.70265\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electronics Letters\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1049/ell2.70265\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electronics Letters","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/ell2.70265","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

提出了一种具有转换完成检测功能的低功耗感测放大器触发器。通过替换逻辑功能，所提出的检测电路可以有效地集成到SA和锁存器设计中，从而显着减少面积，同时降低功耗并确保在低电压下可靠运行。在台积电16nm CMOS工艺中实现的布局后仿真结果表明，在0.4 V的工作电压和25%的开关活性下，与之前的设计相比，所提出的设计功耗降低了25.8%，面积节省了38.7%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

A Sense-Amplifier Flip-Flop With Transition Completion Detection Scheme in 16nm for Low-Voltage and Low-Area Applications

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A Sense-Amplifier Flip-Flop With Transition Completion Detection Scheme in 16nm for Low-Voltage and Low-Area Applications

A low-power sense-amplifier (SA) flip-flop (FF) with transition completion detection is proposed for low-voltage applications. By replacing logic functions, the proposed detection circuit can be efficiently integrated into SA and latch designs, leading to a significant reduction in area while reducing power and ensuring reliable operation at low voltage. The post-layout simulation results implemented in the TSMC 16-nm CMOS process show that, at an operating voltage of 0.4 V and a switching activity of 25%, the proposed design achieves a 25.8% reduction in power and up to 38.7% area savings compared to previous designs.

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来源期刊

Electronics Letters 工程技术-工程：电子与电气

CiteScore

2.70

自引率

0.00%

发文量

268

审稿时长

3.6 months

期刊介绍： Electronics Letters is an internationally renowned peer-reviewed rapid-communication journal that publishes short original research papers every two weeks. Its broad and interdisciplinary scope covers the latest developments in all electronic engineering related fields including communication, biomedical, optical and device technologies. Electronics Letters also provides further insight into some of the latest developments through special features and interviews. Scope As a journal at the forefront of its field, Electronics Letters publishes papers covering all themes of electronic and electrical engineering. The major themes of the journal are listed below. Antennas and Propagation Biomedical and Bioinspired Technologies, Signal Processing and Applications Control Engineering Electromagnetism: Theory, Materials and Devices Electronic Circuits and Systems Image, Video and Vision Processing and Applications Information, Computing and Communications Instrumentation and Measurement Microwave Technology Optical Communications Photonics and Opto-Electronics Power Electronics, Energy and Sustainability Radar, Sonar and Navigation Semiconductor Technology Signal Processing MIMO