{"title":"基于130nm CMOS低压级联编码浮动逆变放大器的sub - 1v 90db - sndr功率/BW可扩展DTDSM","authors":"Xinjie Wu;Yuyan Liu;Zhangming Zhu;Xiaopeng Yu;Nick Nianxiong Tan;Zhong Tang","doi":"10.1109/TCSI.2025.3531666","DOIUrl":null,"url":null,"abstract":"This paper presents a sub-1V delta-sigma modulator (DSM) with power and bandwidth (BW) scalability for IoT applications. It is built around a fully dynamic and low-voltage floating inverter amplifier (LVFIA). To extend the power and BW scalability of the LVFIA, its relatively supply-independent bias current is auto-controlled by DSM’s sampling frequency <inline-formula> <tex-math>$f_{s}$ </tex-math></inline-formula>. Dynamic techniques such as auto-zeroing and chopping are applied to achieve low noise. Fabricated in a 130nm CMOS, the proposed sub-1V DSM shows a near-consistent SNDR (~90dB) and linearly scalable power and BW (2.5nW/Hz) over a <inline-formula> <tex-math>$\\times 30$ </tex-math></inline-formula> scaling range of <inline-formula> <tex-math>$f_{s}$ </tex-math></inline-formula>. It achieves Walden FoM and Schreier FoM of 51.3fJ/conv-step and 175.7dB, respectively.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"1976-1986"},"PeriodicalIF":5.2000,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Sub-1 V 90 dB-SNDR Power/BW Scalable DTDSM Using Low-Voltage Cascoded Floating Inverter Amplifiers in 130 nm CMOS\",\"authors\":\"Xinjie Wu;Yuyan Liu;Zhangming Zhu;Xiaopeng Yu;Nick Nianxiong Tan;Zhong Tang\",\"doi\":\"10.1109/TCSI.2025.3531666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a sub-1V delta-sigma modulator (DSM) with power and bandwidth (BW) scalability for IoT applications. It is built around a fully dynamic and low-voltage floating inverter amplifier (LVFIA). To extend the power and BW scalability of the LVFIA, its relatively supply-independent bias current is auto-controlled by DSM’s sampling frequency <inline-formula> <tex-math>$f_{s}$ </tex-math></inline-formula>. Dynamic techniques such as auto-zeroing and chopping are applied to achieve low noise. Fabricated in a 130nm CMOS, the proposed sub-1V DSM shows a near-consistent SNDR (~90dB) and linearly scalable power and BW (2.5nW/Hz) over a <inline-formula> <tex-math>$\\\\times 30$ </tex-math></inline-formula> scaling range of <inline-formula> <tex-math>$f_{s}$ </tex-math></inline-formula>. It achieves Walden FoM and Schreier FoM of 51.3fJ/conv-step and 175.7dB, respectively.\",\"PeriodicalId\":13039,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems I: Regular Papers\",\"volume\":\"72 5\",\"pages\":\"1976-1986\"},\"PeriodicalIF\":5.2000,\"publicationDate\":\"2025-01-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems I: Regular Papers\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10856716/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems I: Regular Papers","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10856716/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A Sub-1 V 90 dB-SNDR Power/BW Scalable DTDSM Using Low-Voltage Cascoded Floating Inverter Amplifiers in 130 nm CMOS
This paper presents a sub-1V delta-sigma modulator (DSM) with power and bandwidth (BW) scalability for IoT applications. It is built around a fully dynamic and low-voltage floating inverter amplifier (LVFIA). To extend the power and BW scalability of the LVFIA, its relatively supply-independent bias current is auto-controlled by DSM’s sampling frequency $f_{s}$ . Dynamic techniques such as auto-zeroing and chopping are applied to achieve low noise. Fabricated in a 130nm CMOS, the proposed sub-1V DSM shows a near-consistent SNDR (~90dB) and linearly scalable power and BW (2.5nW/Hz) over a $\times 30$ scaling range of $f_{s}$ . It achieves Walden FoM and Schreier FoM of 51.3fJ/conv-step and 175.7dB, respectively.
期刊介绍:
TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.