Optimizing reliability and performance in Re-G-CJNFe-FETs: The role of gate work function and high-k dielectrics in analog and linearity innovations

This study investigates the impact of gate work function (Φ_M) and recessed gate (Re-G) dielectric (ε_o) variations on the analog and linearity parameters of proposed recessed gate Cylindrical Junctionless Nanowire Ferroelectric Field Effect Transistors (Re-G-CJNFe-FETs), across devices D₁ to D₅. The architecture ensures 360-degree electrostatic control, reducing short-channel effects (SCEs), improving scalability, and enabling steep-slope switching for ultra-low-power operation. The analysis is conducted by evaluating key analog performance metrics such as drain current I_ds, OFF Current I_OFF, switching ration (I_ON/I_OFF), transconductance (g_m), and threshold voltage (V_th) under varying work functions (Φ_M = 5.26, Φ_M = 5.1, Φ_M = 4.9, Φ_M = 4.7) and dielectric materials (SiO₂, HfO₂, Al₂O₃, and TiO₂).The findings reveal that reducing the Φ_M from D₁ to D₅ significantly influences I_ds, I_OFF, and subthreshold slope (SS), with notable improvements in V_th and drain induced barrier lowering (DIBL). Similarly, replacing SiO₂ with high-k dielectrics enhances linearity metrics, including second and third-order transconductance coefficients (g_m2, g_m3), and third-order intermodulation distortion (IMD₃) These results are pivotal for designing energy-efficient and high-performance transistors for analog and RF applications. However, ongoing research into material engineering and device architectures continues to push the boundaries, making ferroelectric CJ-NFe-FETs, a viable candidate for next-generation semiconductor technology.