Real-Time SER Measurements of CMOS Bulk 40- and 65-nm SRAMs Combined With Neutron Spectrometry at the JET Tokamak During Its Final D-T Plasma Operation

We performed soft error rate (SER) characterization of 40- and 65-nm bulk CMOS static random access memories (SRAMs) combined with neutron spectrometry in the deuterium-tritium (D-T)-fueled Joint European Torus (JET) tokamak during its final D-T plasma operation (September and October 2023) producing a series of several dozens of power pulses. Our experimental results demonstrate the impact of machine operation on the electronics’ reliability, emulating realistic conditions for circuits exposed to the partially radiation-shielded environment of future fusion reactors. Typical bit-flip (BF) rates of 493 h ${}^{-1} \cdot $ Gbit−1 for 65-nm SRAMs and 2342 h ${}^{-1} \cdot $ Gbit−1 for 40-nm SRAMs were measured for a residual machine-induced neutron flux of $\sim 3.15\times 10^{5}$ cm ${}^{-2} \cdot $ s−1 below the reinforced concrete slab (thickness of 1045 mm) supporting the tokamak chamber. To complete this characterization work, a general methodology for the SER prediction in such a mixed-field D-T neutron radiation environment composed of both thermal and fast neutrons (FN) (up to 14 MeV) is presented and validated from this ensemble of experimental data for the two SRAM technologies. Finally, the interest in this approach for future tokamaks and high-energy physics accelerators is discussed.