基于优化电压缩放电路的互补电压-时间变换器

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Bo-Wei Shih;Ying-Chun Chen;Jia-Yi Lee;Woei-Luen Chen
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引用次数: 0

摘要

延迟线经常面临输入输出非线性和电压时间增益过大的挑战,导致不准确的电压指示和有限的输入电压范围。本文提出了一种具有优化电压缩放电路的互补电压-时间转换器(VTC)来解决这些问题。互补的VTC同时利用输入电压源和输入电压参考延迟线。虽然每条延迟线都有固有的非线性,但它们各自的电压时间增益的相反符号有效地降低了整体非线性。为了进一步提高性能,优化了电压缩放电路,改善了非线性并扩大了输入电压范围。采用UMC 0.18- $\mu $ m技术的实验结果表明,所提出的电路具有良好的线性度,扩展了近轨到轨的输入电压范围,并且对工艺变化具有鲁棒性。VTC的电压时间增益为13.27 ps/mV,信噪比和失真比(SNDR)为32.4 dB,并在整个工作频段保持稳定的动态性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Complementary Voltage to Time Converter With Optimized Voltage Scaling Circuit
Delay lines often face challenges due to input-output nonlinearity and excessive voltage-to-time gain, leading to inaccurate voltage indications and a limited input voltage range. This article presents a complementary voltage-to-time converter (VTC) with an optimized voltage scaling circuit to address these issues. The complementary VTC utilizes both input-voltage-sourced and input-voltage-referenced delay lines. Although each delay line has inherent nonlinearities, the opposite signs of their respective voltage-to-time gains effectively reduce the overall nonlinearity. To further enhance performance, an optimized voltage scaling circuit is incorporated, refining nonlinearity and expanding the input voltage range. Experimental results using UMC 0.18- $\mu $ m technology demonstrate that the proposed circuit achieves excellent linearity, an extended nearly rail-to-rail input voltage range, and robustness against process variations. The VTC achieves a voltage-to-time gain of 13.27 ps/mV, signal to noise and distortion ratio (SNDR) of 32.4 dB, and maintains stable dynamic performance across the working frequency band.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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