用于80-GS/s电缆脉冲响应测量的片上低成本平均数字采样示波器

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Won Joon Choi;Myungguk Lee;Junung Choi;Jaeik Cho;Gain Kim;Byungsub Kim
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引用次数: 0

摘要

确定信道的特性是设计高速链路系统的基本步骤。通过确定信道的属性,设计人员可以深入了解如何以低失真传输信号并优化收发器架构。由于通道的特性可以通过分析其单比特脉冲响应(PR)来识别,因此获得准确的PR图对于可靠的通道表征至关重要。因此,最好就地测量PR,以尽量减少寄生效应。在这项工作中,我们介绍了一种新的原位测量PR的方法,旨在快速准确地生成无失真的绘图结果。为了证明该方法的有效性,我们设计了片上采样范围电路,并制作了28纳米CMOS技术的测试芯片。虽然能够测量无失真的PR,但该方法的脉冲采集速率比现有技术快10倍以上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses
Determining a channel’s characteristics is a fundamental step for designing a high-speed link system. By identifying the properties of the channel, designers can gain insights into how to transmit a signal with low distortion and optimize a transceiver’s architecture. As the channel’s characteristics can be identified by analyzing its single-bit pulse response (PR), obtaining an accurate PR plot is critical for reliable channel characterization. Therefore, it is preferred to measure the PR in situ to minimize the parasitic effects. In this work, we introduce a novel approach for measuring PR in situ, designed to quickly and accurately generate undistorted plot results. To prove the efficacy of the proposed method, we designed an on-chip sampling scope circuit and fabricated a test chip in 28-nm CMOS technology. While being able to measure a distortion-free PR, the proposed method demonstrates a more than $10^{5}$ times faster pulse acquisition rate than prior arts.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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