用于提高系统ECC可靠性的片上BCH故障绑定码

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-01-07 DOI:10.1109/TVLSI.2024.3523899

Seongyoon Kang;Chaehyeon Shin;Jongsun Park

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引用次数: 0

摘要

虽然连续动态随机存取存储器（DRAM）扩展可能需要具有增强纠错能力的片上纠错码（ECC），但尚未探索具有故障边界的双纠错码方案。在本文中，我们提出了一种故障绑定的片上Bose-Chaudhuri-Hocquenghem （BCH）代码，该代码提高了与双数据速率5 （DDR5）双列存储模块（DIMM）中使用的单符号纠错系统ECC的兼容性。该译码方法通过修改BCH码的H矩阵，确定突发错误发生的故障边界，有效防止突发错误跨故障边界传播。有界率与传统码的比较说明了与系统ECC的增强兼容性。所提出代码的编码器和解码器已使用28纳米CMOS工艺实现，以演示硬件成本。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Fault Bounding On-Die BCH Codes for Improving Reliability of System ECC

While continuous dynamic random access memory (DRAM) scaling may require an on-die error correction code (ECC) with enhanced correction capability, a double error correcting code with fault bounding scheme has not been explored. In this brief, we present the fault bounding on-die Bose-Chaudhuri–Hocquenghem (BCH) code that improves the compatibility with one-symbol error correcting system ECC used in dual data rate five (DDR5) dual in-line memory module (DIMM). By modifying the H matrix of BCH code, the proposed decoding method determines the fault boundary within which burst errors occur, effectively preventing the spread of these errors across fault boundaries. A comparison of bounded rates with conventional codes illustrates the enhanced compatibility with system ECC. The encoder and decoder of the proposed code have been implemented using a 28-nm CMOS process to demonstrate the hardware cost.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.