采用无冲突内存访问方案的可扩展低成本 NTT 架构

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-01-15 DOI:10.1109/TVLSI.2025.3526261

Zhenyang Wu;Ruichen Kan;Jianbo Guo;Hao Xiao

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引用次数: 0

摘要

本文提出了一种可变数论变换（NTT）的可扩展多阶段多路径架构。所提出的架构采用多条并行路径，每条路径都使用级联的基数2蝴蝶单元（bfu）。基数-2方案简化了控制逻辑，级联BFU结构减少了RAM组的数量和内存访问频率。此外，提出了一种无冲突且硬件友好的就地内存映射方案，以简化对多条路径的适应，使其能够针对各种吞吐量进行扩展。与现有的产品相比，所提出的体系结构使用的资源更少，在不影响吞吐量的情况下具有更好的区域时间产品性能。

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Scalable and Low-Cost NTT Architecture With Conflict-Free Memory Access Scheme

This brief proposes a scalable multistage and multipath architecture for variable number-theoretic transform (NTT). The proposed architecture adopts multiple parallel paths, each of which uses cascaded radix-2 butterfly units (BFUs). The radix-2 scheme simplifies the control logic and the cascaded BFU structure reduces the amount of RAM banks and the frequency of memory accesses. Moreover, a conflict-free and hardware-friendly in-place memory mapping scheme is proposed to ease the adaption to multiple paths, letting it be scalable for various throughputs. Compared with state-of-the-art works, the proposed architecture uses fewer resources and has better area-time product performance without penalty in throughput.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.